Electronics Forum | Mon Mar 06 17:57:39 EST 2006 | slthomas
Not here, but I'd be interested in hearing what you found.
Electronics Forum | Wed Mar 08 12:38:51 EST 2006 | moonshine
On my site and in my book, there is considerable information answering all your questions. Visit http://www.moonmanondarkside.com and choose your area of interest. All information listed is free. MoonMan
Electronics Forum | Fri Mar 03 16:05:42 EST 2006 | Chris
Hi, Anyone ever perform a DOE on prepreg glass bundle direction or glass bundle grain and how or if it affects PCB warpage and chip component cracking at V-score depanel? Since most FR4 and prepreg has has 1.4 times more fiber bundles in one direct
Electronics Forum | Tue Aug 31 20:41:45 EDT 1999 | Dreamsniper
| | I am looking for a rule of thumb regarding the maximum ramp standard components (chip capacitors) can tolerate without failure during the reflow process. The standard seems to be 3C\second, but this figure is generally derived from the average r
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