Electronics Forum | Thu Feb 24 13:20:40 EST 2000 | Horace Johnson
What software package out there that can manage WIP. We are in the process of consolidating two of our SMT lines into three individual lines for equipment utilization. This will create lots of WIP and need a way to manage it. Any ideals
Electronics Forum | Thu Feb 24 11:02:29 EST 2000 | mark scheunemann
I am looking to discuss 0402 issues, specifically tombstoning/unsoldered. Any recommendations on pad size/spacing, stencil design etc would be helpful. Placement and reflow profile look good.
Electronics Forum | Thu Feb 24 12:08:13 EST 2000 | JAX
Mark, This topic has been discussed multiple time on this site. You can find almost all of them by searching the archives for tombstoning. That aside, have you look at your stencil apetures?(homeplate design).
Electronics Forum | Fri Feb 25 11:32:50 EST 2000 | Michael Parker
Hello Brandy- I would like to suggest that Job location be included in the brief description of each job posting. Thank you, Michael
Electronics Forum | Thu Feb 24 12:06:36 EST 2000 | Casimir Budzinski
First you need to call your flux supplier an find out what your top side board temp should be for the flux you are using and what the dwell time should be.
Electronics Forum | Fri Feb 25 14:41:12 EST 2000 | C.K.
http://www.smtnet.com/electronicsforum/view_message.cfm?message=0007291#7291 * See a past message of mine ! * ...can be found in the archives.
Electronics Forum | Wed Feb 23 17:03:01 EST 2000 | CFraser
What machine are you using to place the components? I assume that you have checked placement prior to the refow process?
Electronics Forum | Wed Feb 23 21:38:26 EST 2000 | Dave F
Mike: I'm with you. The only variable is the component. Look for corrosion, uneven plating, or crud on one of the end-caps. Good luck. Dave F
Electronics Forum | Thu Feb 24 11:33:10 EST 2000 | Michael Parker
Thanks to all who responded. I am tending to believe oxidation is the root cause. I will be contacting the supplier to get definitive answer. Mike
Electronics Forum | Wed Feb 23 16:25:33 EST 2000 | John
We are using a glue and wave solder process for primarily chip components. Our products do not use any fine pitch components. What would an acceptable benchmark for the placement defect rate be? 50 DPMO? 100 DPMO? 200 DPMO? Thanks in advance,
