Electronics Forum: 4.2.2 (Page 1 of 2)

J-STD-001 Par 4.2.2 Temperature and Humidity

Electronics Forum | Wed Jul 11 14:44:21 EDT 2007 | fredericksr

Hi folks! Has anyone ever successfully verified adequate ESD control at

J-STD-001 Par 4.2.2 Temperature and Humidity

Electronics Forum | Wed Jul 18 11:49:59 EDT 2007 | davef

The auditor may be using "verify" in an ESD Program context. See ANSI/ESD S20.20 [1999], 6.1.3, Compliance Verification Plan. It gives one definition of what the auditor may be seeking. For more on verification programs, look here: http://www.protek

J-STD-001 Par 4.2.2 Temperature and Humidity

Electronics Forum | Wed Jul 18 10:35:41 EDT 2007 | hussman

This seems like an odd request from an auditor. I can see an auditor requiring proof that you meet the J-Std, but verify? This would require you purposely damage product on a "before and after" scenario. As long as your manufacturing guideline say

J-STD-001 Par 4.2.2 Temperature and Humidity

Electronics Forum | Mon Jul 16 15:44:27 EDT 2007 | davef

J-STD-001 doesn't necessarily require additional controls under conditions of low humidity, only that you verify the effectiveness of what you have in place. ESD S20.20 [1999] only says that relative humidity above 30% is "desirable". ESD S20.20 [200

J-STD-001 Par 4.2.2 Temperature and Humidity

Electronics Forum | Tue Jul 17 21:48:09 EDT 2007 | davef

Per ESD Handbook TR 20.20 paragraph 5.3.15 Humidity "Humidity is beneficial in all ESD Control Program Plans. Contact and separation of dry materials generates greater electrostatic charges than moist materials because moisture provides conductivity

Moisture Sensitive part - baking

Electronics Forum | Thu Aug 30 09:56:16 EDT 2007 | blnorman

According to J-STD-033 Table 4-1, the bake out time to restore the clock to zero is not only determined by the MSL level, but the package thickness as well. Section 4.2.2 states "SMD packages shipped in low temperature carriers may not be baked in t

J-STD-003

Electronics Forum | Fri Feb 15 14:38:59 EST 2013 | bmario

Hi, We are having a problem with the interpretation of the surface evaluation criteria of J-STD-003 section 4.2.2.4.2. "A minimum of 95% of each of the surfaces (i.e. each pad) being tested shall exhibit good wetting. The balance of the surface may

Re: Wave Solder balls

Electronics Forum | Tue Nov 03 16:28:21 EST 1998 | Dave F

Well my process is I'm running my belt speed at 3.50fpm and about 215 to 225 degrees top side. I got my main wave down to a little less than half the board thickness. I'm not using a hot air knife cause we thought it might create more of a problem

SMT room environment

Electronics Forum | Tue Jan 10 16:01:20 EST 2017 | davef

A review document for J-STD-001F with Amendment 1 had the following wording, but you should check the actual document to be sure of correctness 4.2 Facilities Cleanliness and ambient environments in all work areas shall [D1D2D3] be maintained at le

Upside Down Chips

Electronics Forum | Thu Mar 15 03:24:48 EST 2001 | Scott B

We are currently having a conflict of opinion with our QA department regarding the very few occurences we have of chip resistors being soldered upside down (i.e. the resistive element towards the board). IPC-A-610C para 12.3.2 specifies that this co

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