Electronics Forum | Thu Jul 08 12:33:52 EDT 1999 | Mike Demos
Thank you all for your replies. Thanks to your replies and backup from the IPC-SM-782A (section 3.6.3.2) and James Blankenhorn's "SMT Design Rules & Standards," the designer has agreed to provide adequate clearance between the via and the pad. I wi
Electronics Forum | Fri Jan 21 14:51:08 EST 2000 | Dave F
Mike: I�d hate to see you making design decisions, based solely on the discussion here, but that this would be an impetus to consult IPC-D-279, "Design Guidelines ... " and take a course on designing reliable boards. Werner Engelmaier (Engelmaier
Electronics Forum | Thu Jun 08 01:46:00 EDT 2023 | camilleyang3
To prevent BGA (Ball Grid Array) issues related to SMT (Surface Mount Technology) solder resist when fabricating a PCBA (Printed Circuit Board Assembly), you can follow these guidelines: Design considerations: Ensure proper spacing between BGA pads
Electronics Forum | Thu Oct 26 13:10:48 EDT 2000 | ptvianc
Yes, one should always be concerned about "field failures" because they represent the point at which the product has exceeded its design lifetime with respect to its service conditions. Hybrid microciruit technolgy (HMC) has been around for a long t
Electronics Forum | Wed Aug 22 21:11:25 EDT 2001 | davef
When it works right, it's a beautious thing. => When goes wrong, you have one board with some of the other board's material, not too coo. Scribed and broken ceramic has bad-butt sharp edges. You'll feel this sticky stuff on your hands, look down,
Electronics Forum | Wed Oct 06 00:26:04 EDT 1999 | Karlin
| Hi, | | Help! Could anyone help to enlighten me on this? | | Question: | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z that using a normal water cl
Electronics Forum | Wed Oct 06 08:41:42 EDT 1999 | Dave F
| | Hi, | | | | Help! Could anyone help to enlighten me on this? | | | | Question: | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z that using a n
Electronics Forum | Wed Jul 07 14:14:03 EDT 1999 | Dave F
| Is anyone aware of some guidelines regarding through-hole in SMT pads? One of our designers wants to add through-hole leads in some SMT pads for an inductor. The size of the hole is 0.032 inches and takes-up approximately 25% of the pad area. Th
Electronics Forum | Tue Mar 13 17:26:07 EST 2001 | blair
1) We could press on BGAs and the boards would boot 2) This is basic boot up yield 3) We are now getting stpe by step inspection data going fwd. 4) So, Stencil design could be a critical factor. Any documented guidelines? 5) Yes DFX was done - mostl
Electronics Forum | Fri Oct 08 02:31:07 EDT 1999 | Brian
| | | | Hi, | | | | | | | | Help! Could anyone help to enlighten me on this? | | | | | | | | Question: | | | | | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowab
