Electronics Forum | Mon Apr 16 10:55:01 EDT 2001 | genny
Happened at my company lots on our older designs. We touched up those pads in house by hand, because the solder joint was very poor. We also did it on SOT 86 pkgs on the gnd pins. When they were touched up, we would get an extra 1/2dB of gain out
Electronics Forum | Tue Jun 26 22:52:27 EDT 2001 | ianchan
I second that juicy bit from brownsj, Sn96/Ag4 process is what we are using too, currently for BIB runs, dunno about current capital investments needs, coz from what I understand, our company's BIB pioneer guy, personally designed the machines in cur
Electronics Forum | Wed Jul 18 11:19:58 EDT 2001 | genny
I didn't wade thru all of the info you presented above, but your comment about ampacity of printed circuit boards brought to mind a copy of an article I keep in my files. Luckily I photocopied the whole page from the magazine and can actually tell y
Electronics Forum | Wed Sep 29 04:33:35 EDT 1999 | Earl Moon
| | Hi All, | | Any one experince BGA-chipset warp about 10-15mil after removing | | from PCB? | | FYI, the rework temperature for preheat was 170C from room | | temperature about 30 seconds, & BGA was removed at temperature | | between 190-200C.
Electronics Forum | Mon Sep 13 04:17:10 EDT 1999 | Earl Moon
| I noticed that some of our pcb's component legend/designation are unreadable as they are placed under smt pads. Is this correct and according to standard? Although we don't have any problems with them as of now, I would like to know the effects on
Electronics Forum | Mon Aug 16 16:45:49 EDT 1999 | Scott Cook
| We have a design on which there is an ASIC that will not be produced anymore in the future. As we want to make this design over the next 10 years we are evaluating the possibility to buy the necessary ASICs for the next 10 years. This will give us
Electronics Forum | Fri Jul 30 11:16:55 EDT 1999 | DLKearns
| I have been asked to supply a maximum shelf life for our assemblied PCB's. I realise this is dependent on so many factors- temperature, humidity, no of layers etc. But does anyone have a formulae for calculating shelf life, or does anyone know of a
Electronics Forum | Thu Jul 08 12:33:52 EDT 1999 | Mike Demos
Thank you all for your replies. Thanks to your replies and backup from the IPC-SM-782A (section 3.6.3.2) and James Blankenhorn's "SMT Design Rules & Standards," the designer has agreed to provide adequate clearance between the via and the pad. I wi
Electronics Forum | Wed Jun 09 13:11:29 EDT 1999 | John Thorup
| In past PCB designs I have cleared all traces from all layers | (except pwr/gnd) from fiducial area. It has come to my attention that this is only necessary on the side where fud is placed. Which is the correct method of design using a fidicial?
Electronics Forum | Fri Feb 19 09:29:38 EST 1999 | Justin Medernach
| What to look for that causes tombstoning and the corective action. | The three biggest causes that I can think of are placement machine component picking inaccuracy, placing inaccuracy, and design design design. If your placement platform is pic
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