Electronics Forum | Wed Jul 14 11:36:56 EDT 1999 | Jimmy Strain
| | | Hi All, | | | Does any one experienced the solder on gold finger after | | | reflow. Its about 5 to 8 mils diameter . | | | We'd clean the entire screen printer, mounter & reflow as well, | | | but doesn't help much. | | | | | | | | Mr Kong..
Electronics Forum | Fri Jul 02 10:06:17 EDT 1999 | John Thorup
| | | | We are wave soldering some fabs with a lot of unmasked trace area along the edges. The trace area is solid copper covered with tin / lead, no masking, no components along the edges, same on solder side and component side (goofy board design)
Electronics Forum | Wed Mar 17 21:42:19 EST 1999 | Chuck Garth
We are presently aluminum wirebonding to gold plated lands. Our board manufacturer has been very inconsistient in the quality. It seems as though theey are over etched by about half the amount they should be. Can anyone give me the spec's that normal
Electronics Forum | Tue Jan 19 12:25:23 EST 1999 | Mike Cox
I need some opinions (And I know everybody has one). I am mounting a board into a case, after mounting the board I am loading it with stress in the middle causing it to bend around .030 inch. The board is 4" X 6" and is Bending in the 4" direction.
Electronics Forum | Fri Nov 27 02:09:50 EST 1998 | Chi-Ting Chen
| | I have some 1.25 mils Al wire bonding chip on board process. After epxoy-based encapsulation, I do some aging test. How can I "see" or prove that there is a "wire break" exist due to the tension of thermal cycling? How can I know the failure is c
Electronics Forum | Fri Nov 27 02:11:17 EST 1998 | Chi-Ting Chen
| | I have some 1.25 mils Al wire bonding chip on board process. After epxoy-based encapsulation, I do some aging test. How can I "see" or prove that there is a "wire break" exist due to the tension of thermal cycling? How can I know the failure is c
Electronics Forum | Wed Sep 30 11:57:19 EDT 1998 | Manish Ranjan
Hi Everybody Is anyone aware of the possible causes that may lead to voids in the solder bumps after assembly. We assembled some dice on thin substrates and after assembly, void formation in the solder bumps were observed. We have already trie
Electronics Forum | Wed Sep 30 11:56:46 EDT 1998 | Manish Ranjan
Hi Everybody Is anyone aware of the possible causes that may lead to voids in the solder bumps after assembly. We assembled some dice on thin substrates and after assembly, void formation in the solder bumps were observed. We have already trie
Electronics Forum | Wed Aug 12 07:31:37 EDT 1998 | Earl Moon
| We are taking enquiries for sub-contract work that we hope to be doing by Christmas. One of the enquiries is to assemble chip capacitors and an SO14 onto ceramic. Does the printing process, paste used and reflow process remain the same, or are ther
Electronics Forum | Wed Jul 29 22:50:17 EDT 1998 | Dave F
| We are investigating alternatives to HASL finishes for more dense PWBs. OSP is not a good choice because of low solid flux and possibly long shelf life. Immersion gold is expensive and so far has been more difficult to wave solder. Has anyone ha
