Electronics Forum | Tue Oct 23 09:09:27 EDT 2001 | Cemal Basaran
What is the reflow temperature you use to attach this package to your PCB.? I did extensive study on this package and compared it with other packages. I used our own Moire Interferometry, SEM, EDX studies. In my opinion the problem is TI does not man
Electronics Forum | Thu Oct 25 21:04:18 EDT 2001 | davef
You are correct. So, the unit amount of gold [based on IG plating thickness, size of the pad, etc.] dissolves in the solder very quickly. When the solder is liquid for: * A long time, the gold disperses more. * A short time, the gold concentrates a
Electronics Forum | Tue Oct 30 14:54:26 EST 2001 | jhingtgen
Doug, Thank you for your interest in DEK's PumpPrint technology. The stencils are a plastic type with a standard thickness of 3mm. This thickness, as you mentioned is to allow us to route out for clinched leads. Also for note is that we manufactu
Electronics Forum | Wed Oct 24 02:19:34 EDT 2001 | Leo Gapasin
We have been monitoring our solder defects at post-SMT, post-Wave, etc.in our plant. I want to compare our process performance to a "bench mark" for solder defects at post-SMT. The question I have is what is the "bench mark" for soldering defects in
Electronics Forum | Fri Nov 09 14:23:12 EST 2001 | vickt
You are correct...These are proprietary codes. Your best bet is to stick to the UCT-31. Other folks have tried to create a tool of their own, but have had little success. Universal Instruments offers component library conversion tools as well as patt
Electronics Forum | Thu Oct 25 04:52:17 EDT 2001 | Vai
I'm running intrusive reflow. What happened was when the board went thru' the first reflow ( which is secondary side ), at Post reflow, I can see the solder joint quality is very good smooth and shiny. But when we proceed with the 2nd reflow, at Post
Electronics Forum | Mon Oct 29 16:34:02 EST 2001 | patcope1
I have a custom connector that tends to lift during reflow. The PCB retention tabs and pins are lifting off of the pads on the board and the solder is forming underneath the pads, with no heel or toe filet. Is there anyone out there that can help if
Electronics Forum | Mon Oct 29 18:21:43 EST 2001 | slthomas
We recently have received a lot of warped (bowed and/or twisted behond IPC 600 specs.) bare boards (some our fabricator's fault, some ours by design) and I can't help but figure that long term reliability will suffer when building product with them.
Electronics Forum | Mon Oct 29 20:19:44 EST 2001 | davef
DON'T do it!!! The two problems you'll have are: 1 Poor manufacturing process control, resulting in weak solder connections. 2 Weak solder connections are stressed, when the board is straightened upon installation in the "box". There's several hits
Electronics Forum | Tue Oct 30 19:42:44 EST 2001 | davef
Jim Blankenhorn [www.smtplus.com] has the best understanding of designing pads for real life. That�s because he designs them like he wants to design them and doesn�t negotiate with a committee of thousands for an IPC standard. Consider doing this
