Electronics Forum | Wed Apr 04 08:28:27 EDT 2001 | Cal
ZAM_BRI- I don't know how effective this may be but some points to include in the buy-off procedure: Before submitting the PO for the stencil you may also want to do a CAD to Stencil comparison to verify correct apertures.There are SW packages and co
Electronics Forum | Thu Apr 12 03:55:06 EDT 2001 | surachai
Dear anyone ; Every time that we run profile now ,we will create profile from recommendation of vendor flux and the some critical parameters such as thermal shock or others ... but I don't know that Do you ever create standard profile to be procedure
Electronics Forum | Mon Apr 30 10:48:10 EDT 2001 | CAL
oktayunsal- Machines are your secondary problem. Knowing and understanding SMT process is your biggest obstacle. SMT process involves Electrical, Chemical, Industrial, and mechanical engineering disciplines.As a start I would begin with IPC related
Electronics Forum | Thu Oct 26 18:10:11 EDT 2000 | ptvianc
Philip: Cases 1-3, those criteria may be specified in more recent versions of ANSI/J-STD-001 and/or ANSI/IPC-A-610. Unfortunately, I do not have any new versions of these specs. that may cover these points. As for voids in BGA joints, I have not
Electronics Forum | Thu Jul 20 14:36:57 EDT 2000 | Bob Willis
Yes there will be higher process temperatures on the currently preferred alloys of tin/silver. There are not that many companies highlighting they have the solutions although many parts will be fine. If all components meet the requirements of the IP
Electronics Forum | Thu Jul 20 16:33:13 EDT 2000 | Bill Brooks
Hi Bob, I am a member of the IPC Designer's Council and as the Education officer for our San Diego Chapter, I would like to see more information available to help educate the existing Designers and the students in design classes we are trying to ge
Electronics Forum | Thu Jul 20 16:39:21 EDT 2000 | Bob Willis
There are so many people with this knowlege I would suggest some form of evening class. We did use to do it over here but it did not have many takers. I lecture every year at two universities and schools its great fun and don't you people ask the mo
Electronics Forum | Wed May 09 01:40:55 EDT 2001 | Dreamy
Hi Michael, DPMO Index calculation - The total number of defects (Dc + Dp + Dt) on a completed Printed Circuit Board divided by the total number of defect opportunities (Oc + Op + Ot) for that PBA multiplied by 1 million. Your calculation deals only
Electronics Forum | Fri May 11 10:33:22 EDT 2001 | wbu
Hi KP, I�m wondering why you send those boards outhouse for the SMD part with a stencil. How do you know it fits their printer. We give the stencil data 1:1 to the subcon so that they can order the stencil to their needs with reduction and thicknes
Electronics Forum | Mon Jun 18 11:23:44 EDT 2001 | Gil Zweig
BGA defects observed with x-ray inspection fall into catagories. One catagory is the obvious defects; i.e. soledr bridges, missing balls, excessive solder voids. The second catagory is the more subtle "potential" defect. This is where variations in
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