Electronics Forum: joes (Page 1 of 23)

Open board SiP PCB warpage measurement

Electronics Forum | Fri Aug 30 11:20:17 EDT 2013 | jth

Hi, contact me at joe@zntechnologies.com. ZN Technologies offers warpage measurement at room temp and during reflow using the superior projection moire technique. Best regards, Joe

Re: problem when testing the RF product

Electronics Forum | Mon Jun 21 12:03:20 EDT 1999 | Scott Cook

Since Vic posted me privately and asked for the SIR test parameters I spoke of in my other post, I thought I'd respond on the forum. Ok, here they are, per Joe Keller--Solder / process consultant AKA Manko..... This is an accelerated SIR / dendrite

Agilis Feeders

Electronics Forum | Thu May 30 14:09:56 EDT 2002 | Roger

What's your real name? Is Joe or John? Regards, Sponge Bob

Fiducial mark

Electronics Forum | Thu Aug 18 18:33:15 EDT 2005 | darby

Search for this posting "Component Location Related to Fiducial Marks" from 9/06/04 by Joe O.B.

Jot destacker

Electronics Forum | Wed Apr 23 20:43:50 EDT 2008 | pfifla1

I have one. contact me at joe.gurley@pfiofflorida.com and i will send pics.

Kester 985M - Will It Help?

Electronics Forum | Tue Nov 26 11:29:19 EST 2013 | joeherz

Patrick, Thanks for the reply and well said. Joe

Sample assembly notes

Electronics Forum | Fri May 27 18:41:35 EDT 2022 | SMTA-64387182

Got it, Thanks, Joe

Sample assembly notes

Electronics Forum | Fri May 27 18:42:16 EDT 2022 | SMTA-64387182

Yes, Those are the notes. Thanks, Joe


Electronics Forum | Fri May 27 18:43:19 EDT 2022 | SMTA-64387182

Thanks for confirming. Joe

ENIG; Au < 0.5 um to avoid solder joint embrittlement

Electronics Forum | Tue Jun 07 20:17:09 EDT 2022 | SMTA-64387182

Understood, Thanks, Joe

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