Electronics Forum | Fri May 01 08:15:36 EDT 2009 | davef
Scavenging Methods [Improve Solder Scavenging of Large Area-array Sites, SMT, Laurence Harvilchuck, process research engineer, Unovis Solutions, harvilch@unovis-solutions.com] Two common methods exist for scavenging residual solder on the site for s
Electronics Forum | Sat Jul 29 09:01:08 EDT 2006 | davef
Well, a "reflothermal recipe" is a typo. It should read "reflow thermal recipe". Sorry for the confusion. Most people call this THE PROFILE. We think a profile is the output of a profiler when it portrays the result of a reflow recipe. We're gue
Electronics Forum | Fri Aug 25 09:12:07 EDT 2006 | russ
When not practical to drill hole into pcb to profile here is what I do and seems to be just fine. place thermo into area underneath BGA and let her rip, you will not be in the ball/solder joint, but the temp difference as long as you are in the arra
Electronics Forum | Thu Jan 09 11:29:41 EST 2014 | spoiltforchoice
Thermal profiling typically requires a profiling kit, this will include a thermally insulated datalogger that follows your PCB through the oven connected to a number of thermocouples which you might affix to your PCB using heat resistant tape or usin
Electronics Forum | Wed Nov 25 21:23:29 EST 1998 | Dave F
| I like to know under what conditions the reflow profile of a solder paste is taken? Bare board, board with the solder paste, or board with high melt solder paste? | John: None of the above. The two key variables that determine the reflow tempera
Electronics Forum | Wed Jul 11 12:26:54 EDT 2001 | mzaboogie
Hi Ian, Answers to your questions: 1) PCB Pad Finishing- HASL 63/37 2)Checked a sample lot of parts. Coplanarity did not seem to be an issue. Some of the parts checked still exibited this condition after reflow. 3) There are no large ground plane
Electronics Forum | Mon Oct 19 17:45:25 EDT 1998 | John Gregory
Dave - I noticed your comment concerning solid solder and was compeled to drop a note. We have developed a process which uses some material characteristics from earlier efforts with this technology and profiled it for flip chip and area array attach
Electronics Forum | Mon Oct 19 17:43:12 EDT 1998 | John Gregory
Ryan - I noticed your comment concerning solid solder and was compeled to drop a note. We have developed a process which uses some material characteristics from earlier efforts with this technology and profiled it for flip chip and area array attach
Electronics Forum | Fri May 20 03:41:04 EDT 2016 | jpcwg
With power components coming in smaller and smaller surface mount packages it is very important to come up with a coherent approach to mitigating the thermal dissipation requirements of these components in a PCB design. While the development of an ex
Electronics Forum | Tue Apr 13 09:46:39 EDT 2004 | davef
Now, that's different. We misunderstood the problem from your original descrtiption. We thought the voids were showing at the via in the pad. Now, we understand the voids appear to be in the solder balls. Suggestions are: * Search the SMTnet Arch
