Electronics Forum | Tue Aug 31 21:45:49 EDT 2004 | KEN
I have experienced this directly in SMT and wave solder. Fillet lift (can) be a direct indicator to lead enrichment (but its not the exclusive symptom). Lead enrichment in smt joints reduces the interfacial strength shortening the time to creep f
Electronics Forum | Tue Nov 28 15:10:50 EST 2006 | M. Sanders
Unfortunately, I don't have a copy of IPC-A-610 D on hand, however, I believe in IPC-610, this �floating height� between lead and pad has no maximum specification restriction. As long as there is no voiding, it is still acceptable for all 3 classes.
Electronics Forum | Fri Mar 26 11:31:34 EDT 2010 | rway
I have been using ICT for a number of years. It is still a viable resource for catching defects in the production process. AOI doesn't catch everything, such as bridging on QFN or J-lead devices (this will depend on the type of AOI and camera syste
Electronics Forum | Mon Mar 29 12:10:14 EDT 2010 | rway
Test Jet will work for catching lifted leads, certainly. X-ray is the only thing for testing for internal solder defects such as voids and cracks. I personally do not have any experience using X-ray, so I cannot advise on its reliability. Perhaps
Electronics Forum | Mon Jan 10 18:35:05 EST 2011 | eadthem
Ive used a Mirtec machine for 3 years MV3L with side angle inspection. Mirtec has some issues documentation, and repair plus. But there machine is impressive and the AOI software is good. We can find about 90-99.99% of all errors using just the 5
Electronics Forum | Fri Nov 18 12:35:15 EST 2011 | rway
As the article eludes to, you still need probe access to measure the pins with TestJet. One thing I wanted to add was the use of JTAG for use with Boundary Scan. Certain devices have JTAG capability, but not all JTAG devices are Boundary Scan compa
Electronics Forum | Mon Sep 22 17:02:58 EDT 2008 | hegemon
You are on the right track Ismir. Essentially however, as the programmer of the machine, I am the one that creates the PCB with the errors to benchmark the settings for the machine. No secret lab though! :-) Easy enough for most any AOI machine to
Electronics Forum | Tue Sep 16 19:16:11 EDT 2008 | hegemon
Hello everyone! > > I'm a student of electrical > engineering currently working on a thesis for my > BSc degree. It will be about post reflow AOIs and > AXIs, and I'd kindly like to ask you for some > help with it. > > I would like to know if t
Electronics Forum | Tue Jul 30 09:50:51 EDT 2019 | ameenullakhan
Attached is the image of lead lift in ccga
Electronics Forum | Mon Jul 18 12:24:53 EDT 2016 | oleksz
Some people involved in PCB assembly process claim that SMD components reflow soldering problems are often caused by traces running under a component. According to this claim, trace (or any copper) covered by solder mask and placed under SMD componen
