Electronics Forum: mil and spec and soldering and acceptance (Page 1 of 1)

J-STD-002 and -003 solderability testing...

Electronics Forum | Sat Jun 30 11:03:29 EDT 2001 | davef

Nice to have you back on SMTnet. Some of the newer folk have missed-out on the solid contributions you�ve made to the Forum. The chicken wire cleaning basket was a classic!!! [It�s a shame that the folk at SMTnet can�t recover those files.] We bu

Pad and Stencil Design

Electronics Forum | Mon Sep 17 16:03:13 EDT 2001 | jschake

The results from an experiment comparing 27 different combinations of pad dimensions concluded that the pad design with 15 mil pad length, 12 mil pad width, and 9 mil pad separation produced the best assembly yields. A 5 mil thick laser cut stencil

Material Ageing and Storage

Electronics Forum | Thu Feb 22 04:00:02 EST 2001 | Scott B

We are increasingly being asked to store components for longer and longer periods which we know through experience leads to reduction or total loss of solderability of the parts. 1) What is the industry accepted shelf life of tin/lead plated compone

seperation of soldermask and pcb

Electronics Forum | Tue Mar 25 11:43:48 EDT 2014 | sara_pcb

It is Solder Mask on Bare copper, The land finish is HASL as per MIL-PRF-55110G which accepts trace of HASL as acceptable. Wetting is acceptable. regards, R.Saravanan

voids- leaded and chip components

Electronics Forum | Fri Jan 23 10:39:35 EST 2004 | patrickbruneel

Kris, I assume with voids you mean acceptable solder coverage of pad and lead. As Dave mentioned I also have not seen any specific studies on voids, but workman ship standards exist about acceptable coverage of pad and lead (both consumer and MIL)

Leaded and Lead-Free Wave Parameters

Electronics Forum | Thu May 22 16:52:39 EDT 2008 | tonyamenson

Indium got back to me with the attached PDF. I always assumed, that in order to avoid thermal shock, there could not be any more than 80 degrees C difference between the solder pot and the pre-heated board. However, it would seem that any thing le

Re: Cracking Capacitors and Solder Balls

Electronics Forum | Mon Jun 08 15:29:17 EDT 1998 | Gary Simbulan

| Earl, et al, | Boy things get old and cold around here fast. I promised more detail on my capactior problem and I thought I could drop something completely different in the same message and tell a tale of solder balls. | First the caps. We stil

Tinned leads and where the component body is defined

Electronics Forum | Thu Sep 03 22:03:32 EDT 2020 | SMTA-64386139

Both conditions are acceptable for this bottom brazed flat pack package. The solder coverage must be within 0.070 inch of the lead/package interface per MIL-PRF-38535, paragraph A3. While that requirement could allow for a gold gap near t

Gold plated board, with csp's and 0603 with no clean apetures

Electronics Forum | Thu Sep 26 14:43:43 EDT 2002 | Jim M.

unsure of what solder spec. your working to?.IPC/EIA J-STD-001C, Section 9.2.4 clearly states dull, matte, gray or grainy appearing solders are accpetable depending on your process and if the acceptability of the neaxt paragraph is met.IPC 610 and J-


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