Electronics Forum | Sun Jan 24 06:44:31 EST 1999 | Kallol Chakraborty
| | Could anyone send me equations to calculate controlled impedance of traces on circuit boards. I am most interested in the buried traces in multi layer boards. | | | | Thanks, | | David - piengr@verinet.com | | | As one of the first MLB impedan
Electronics Forum | Fri Jan 15 09:36:20 EST 1999 | Earl Moon
| Folk's, | | I'm looking for information of how long you cna store a gold finish PCB before building it. I know there are problems with the gold disappearing into the underlying nickle over time / temperature etc but exactly how long do you have be
Electronics Forum | Thu Jan 14 22:35:08 EST 1999 | Chris G.
| | I'm looking for a CABGA test socket for a 2 CABGAs. One 81 ball CABGA is 9mm x 9mm with .46 mm dia balls on .8mm pitch. The other is a 64 ball CABGA 8mm x 8mm with .46 mm dia balls on .8mm pitch. I need to pretest CABGAs before placement due t
Electronics Forum | Sun Jan 10 08:44:32 EST 1999 | Dave F
| | | HI! I am a package engineer in Korea. I have some reasons | | | to desolder excessive solder at the lead of TSOP and TSOJ | | | after removing them from the board. The way with solder wick is too time-consuming and depends on the operator. |
Electronics Forum | Tue Jan 05 18:07:53 EST 1999 | Dave F
| I am looking for information regarding post wave soldering of stranded wires into a circuit board using OA core wire solder. We do a final pass thru the cleaner after the hand soldering but I'm concerned about any OA flux residue that may have wic
Electronics Forum | Thu Nov 19 16:24:23 EST 1998 | Earl Moon
| Hello Everybody | | I am new to the electronics packaging arena, please be patient with me... I have a few questions regarding the various passivation used on the silicon dice. I would really appreciate if you guys could provide me with more info
Electronics Forum | Fri Nov 13 09:55:08 EST 1998 | Chrys
| We are experiencing 'lifting' on one or more sides of a QFP. Poor lead co-planarity has been ruled out by independent tests. Please tell me which of the two remaining failure modes is the most probrable? | | 1. Expansion of gases in vias underneat
Electronics Forum | Thu Nov 19 05:25:07 EST 1998 | karlin
| | We are experiencing 'lifting' on one or more sides of a QFP. Poor lead co-planarity has been ruled out by independent tests. Please tell me which of the two remaining failure modes is the most probrable? | | | | 1. Expansion of gases in vias und
Electronics Forum | Thu Oct 29 12:12:48 EST 1998 | Barry Kauffman
| | | | Does anyone know of any software programs that will verify a Pick & Place program to the Bill of Materials (BOM)? Verify meaning the Part # and Ref. Des. matching of the two files. | | | | We use GCPlace to merge our BOM with X/Y file |
Electronics Forum | Thu Oct 01 16:46:50 EDT 1998 | Dave F
We are trying to eliminate/minimize the baking process for high lead-count ICs. We would like to reseal packages containing these parts to minimize exposure to humidity. Anyone have or know of a way to reseal or vacuum pack parts? Any suggested eq
