Electronics Forum: probe marks (Page 1 of 2)

Probe Mark during ICT

Electronics Forum | Fri Jun 01 05:46:12 EDT 2012 | vileo72

Hello friends , What is the extent of Probe mark allowed on a assembled board ? Is there any related material on net or standard .Recently we had an issue where the ICT was done and the joints on which the pins were tested had dents on the joints

Probe Mark during ICT

Electronics Forum | Mon Jun 04 00:38:17 EDT 2012 | vileo72

Hello friends , Any leads !! Regards Vikas

Probe Mark during ICT

Electronics Forum | Mon Jun 04 10:40:37 EDT 2012 | davef

I'm not aware of any such stipulation about witness [probe] marks for assembled boards, per se. Certainly, witness marks should not affect the intended performance of the assembly, you know, like damaging the solder connection or smudging solder mate

Probe Mark during ICT

Electronics Forum | Tue Jun 05 02:22:07 EDT 2012 | vileo72

Dear Dave/pr/Reese, Thank you so much for the information and this will certainly help me to align on the query .Would like to know further :During Flying probe testing the vias are also observed that they have pin mark on the annular ring due to the

Probe Mark during ICT

Electronics Forum | Mon Jun 04 09:32:23 EDT 2012 | pr

IPC-610 should tell you if the joint is suspect. I would tend to think they would not have any negative effect.

Probe Mark during ICT

Electronics Forum | Tue Jun 05 08:40:46 EDT 2012 | rway

How deep is the indent? I would say as long as it is hitting nothing but net (the solder fill), your fine. Besides, you should notice indents on your solder fillets of components on the top-side as well. This is also expected and acceptable.

Probe Mark during ICT

Electronics Forum | Mon Jun 04 23:52:57 EDT 2012 | rway

Actually, if you experience lack of witness marks, you probably have a problem. Witness marks are OK and will not affect your assembly. I assume this is an SMT assembly we are talking about, in which case, this is what your test pads are for. You

Probing Vias

Electronics Forum | Wed Jul 20 15:05:28 EDT 2005 | Fred M.

With the new rev D release of IPC-A_610 came a new section which identifies a via (through hole) with nicks along the inside of the annular ring. Defect is all three classes and states "Damage to conductor or lands". We have for years defa

AOI vs. electrical test

Electronics Forum | Wed Jan 04 12:48:34 EST 2006 | pjc

In-Circuit Test is the best method for ensuring solder joint connections. It is a much more reliable than AOI. An ICT machine can ensure solder connections are made for array package devices such as BGA, PGA, etc... AOI is best for component I.D.- is

In Circuit Test Specs

Electronics Forum | Fri Jun 15 09:59:29 EDT 2001 | brownsj

We have recently had an incident where we feel that we have received a batch of cards from our assembly house which have by-passed their ICT operation. This has been determined by the lack of any indentations on the test pads from the sprung probes.

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