Electronics Forum: process (Page 66 of 1146)

Why is NC the prefer process for BGA mounting? why not WS?

Electronics Forum | Thu Aug 23 00:22:10 EDT 2001 | mugen

Ha! I too have a P.h.D...... Mine is a certified, "PASS. Highschool *with* .Difficulty".... so which rock did you crawl from under??

Why is NC the prefer process for BGA mounting? why not WS?

Electronics Forum | Thu Aug 23 01:23:03 EDT 2001 | mugen

Thanks, for pointing out my lack of, precision inquiry methodology.... I'll keep it in mind, and stay on my toes, next time I post a forum question... Regards

Etch strain gauge in copper layer to measure deformations during press process [How to?]

Electronics Forum | Wed May 14 13:31:22 EDT 2014 | taiji

You should look in to this document: IPC/JEDEC-9704A Printed Circuit Assembly Strain Gage Test Guideline Regards

How to Differentiate Class 3 and Class 2 products in terms of process

Electronics Forum | Tue Jan 06 06:56:26 EST 2015 | stivais

How about rework (touch-up) for Class 3? Some say that you are not allowed to rework anything for Class 3. Though I have not found any proof for this 'requirement' in the standards.

How to Differentiate Class 3 and Class 2 products in terms of process

Electronics Forum | Sat Jan 10 05:55:13 EST 2015 | jandon

Rework is acceptable in class 3 but hardware defects shall be documented before rework and rework shall be documented.

How to Differentiate Class 3 and Class 2 products in terms of process

Electronics Forum | Sat Jan 10 09:04:47 EST 2015 | jandon

class 3 requires 100% barrel fill Class 3 requires 75% vertical fill of solder for component with less or more than 14 leads. Not 100% fill.

No Clean OSP process cause ICT testing issue due to Flux building in testvia hole

Electronics Forum | Fri Mar 29 07:53:12 EDT 2019 | davef

Why are you printing paste on test via? In the old days, we probed soldered pads to cushion impact force of probing. Is that still a reasonable practice?

No Clean OSP process cause ICT testing issue due to Flux building in testvia hole

Electronics Forum | Wed Apr 03 19:02:16 EDT 2019 | SMTA-Vikram

We still use Via as test points. so we need to paste Via. Pasting will make better contact with probes compare to test via without solder.

No Clean OSP process cause ICT testing issue due to Flux building in testvia hole

Electronics Forum | Thu Apr 11 00:58:44 EDT 2019 | SMTA-Vikram

Thanks for info regarding rotating probe head. We do not recommending to use this probes as it may damage bare board as it will pierce thru board and will shorted etches.. Avoid using this probe for PWBA

No Clean OSP process cause ICT testing issue due to Flux building in testvia hole

Electronics Forum | Fri Jun 07 05:19:23 EDT 2019 | gregoryyork

dont usually see this unless the Rosin hasnt been hardened due to low reflow or excessive pressure on blades squeezing flux out so you have flux rich areas. Are these boards also flow soldered?


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