Electronics Forum | Wed Dec 20 14:52:38 EST 2000 | susan
For attribute data, the process capability is reflected by the process average nonconforming (e.g.p bar). Reference the automotive group's AIAG SPC Manual. Hope this helps, Susan
Electronics Forum | Sun Oct 01 05:15:14 EDT 2000 | jarnopy
Maybe best thing is if you rent x-ray machine until that problem is locate. When your process is working then you don't need x-ray machine. Then you must keep every phase of process working.
Electronics Forum | Fri Sep 22 12:47:45 EDT 2000 | John Thorup
Hello Steve There is a wealth of information on this process in the archives. Please search for pin in paste, paste in hole, intrusive reflow, etc. You'll find links to Bob Willis, Amp and Phil Zarrow as well. Many of us use this process daily with
Electronics Forum | Wed Sep 13 20:44:26 EDT 2000 | Dave F
Good question * Rich lathrop at Heraeus wrote a good paper on quantifying the printability of adhesives. You can probably find it on their site. * J-STD-001 is the baseliine for qualifying processes. Good luck
Electronics Forum | Thu Jul 27 21:34:41 EDT 2000 | Dave F
Gary: That's curious. Tell us more about your process steps, temperature profiles, paste, warping of the board without the PIH processing, components, etc
Electronics Forum | Wed Jul 26 15:55:45 EDT 2000 | P. J. O'Connor
We are developing a SMT Process FMEA as part of a "Green Belt/Six Sigma" project. We have searched the web and not found anything that is specifically helpful. Does anyone have a guideline or similar document they might be willing to share?
Electronics Forum | Wed Jul 26 15:55:39 EDT 2000 | P. J. O'Connor
We are developing a SMT Process FMEA as part of a "Green Belt/Six Sigma" project. We have searched the web and not found anything that is specifically helpful. Does anyone have a guideline or similar document they might be willing to share?
Electronics Forum | Tue Mar 07 21:19:50 EST 2000 | Van Hoang Dinh
I have few problems below, 1.I had problem with clean glue stencil at the midle of the process and after the process. 2.Very hard to Fix the bridging on the (close pin) connectors through the wave. Anyone can help on this. Thanks Van
Electronics Forum | Thu Feb 24 13:20:40 EST 2000 | Horace Johnson
What software package out there that can manage WIP. We are in the process of consolidating two of our SMT lines into three individual lines for equipment utilization. This will create lots of WIP and need a way to manage it. Any ideals
Electronics Forum | Thu May 03 17:34:57 EDT 2001 | oscar mendez
Does any one experienced problems on BGA voids related to height of chip (placement), and also another question, Does any one has some statistical process control for the BGA soldering process? if the answer is yes, I'd like to have advice from you.
