Electronics Forum | Fri Jun 20 03:47:24 EDT 2008 | philip
Hi all, any good recommendation for PbF paste application to reduce voids underneath the QFN thermal pad (stencil thickenss? opening? via hole? reflow profile etc)? We have tried few stencil opening design but no significant improvement as seen. Ther
Electronics Forum | Fri Sep 27 15:30:28 EDT 2002 | russ
greetings all Does anybody have any methods or recomendations for removing/reducing excessive voiding in BGAs that are already on board? Had a bad lot of paste and I believe that we are seeing some opens due to very large voids. Any and all input
Electronics Forum | Fri Jun 20 18:32:55 EDT 2008 | hegemon
Back when I used to do a lot of these style devices we ran into the same problem you are describing. Use a pattern for the center pad area and keep the total coverage to about 68% of the pad area. Diagonal Stripes, tic tac toe, cloverleaf, dot array
Electronics Forum | Sat Oct 19 08:33:50 EDT 2002 | johnw
The whole thread seem's to have gone off track. Russ we've been doing a fairly big bit of work on the whole BGA voidign thing as we were so unhappy with the answer's that we were getting from around the industry, basically no one really kows all the
Electronics Forum | Sat Oct 19 11:48:39 EDT 2002 | davef
Good points, John. Continuing to track on the voiding issue, why remove voids anyhow? * Voids are primarily process indicators. There is experimental evidence that voids retard crack propagation locally around the void on at least on a temporary bas
Electronics Forum | Mon Sep 30 20:41:25 EDT 2002 | jason
Hi, The acceptance level for voids is 25% and most of it on your case should be the paste. If you want to reduce / eliminate it, you gotta have the Production to practise FIFO for the usage of the paste. If it is expired paste or exposed to long
Electronics Forum | Tue Mar 19 09:29:08 EST 2002 | Basaran
What type of solder ball defect that you want to avoid is it voids or misregistration or ball-pad adhesion. Cemal Basaran
Electronics Forum | Thu Mar 25 11:30:33 EDT 2010 | Sean
Hello Rajeshwara, If not mistaken, the 25% solder void specification is for BGA...As I I as know, no specification given to mosfet component yet..I think you are right, I need to look at the stencil aperture in order to reduce the air trap underneat
Electronics Forum | Fri Aug 16 10:00:03 EDT 2002 | davef
You have a very bad situation. It�s tough for the gas, flux material, er whatever to escape when the BGA is sitting on top of it and the blind via is blocking it from the other side. Obviously the vias should have been: * Placed on the edge of the
Electronics Forum | Tue May 07 10:13:06 EDT 2019 | cyber_wolf
I have personally never seen a reflow profile change reduce voids. We have invited "experts" in to demonstrate this claim. They were unable to.
