Electronics Forum: solder a (Page 966 of 1481)

Soldering under nitrogen atmosphere

Electronics Forum | Sat Jul 16 13:53:52 EDT 2022 | yannick_herzog

Hello all, we use a reflow oven from Rehm in our SMT production. At the moment we solder under nitrogen atmosphere (approx. 500ppm). Now we want to reduce the nitrogen consumption (costs etc.). What consequences can occur here? Especially on the s

Re: Clean raw bds

Electronics Forum | Mon Aug 17 03:05:59 EDT 1998 | Bob Willis

| | Where can I find a spec to put on my fab drawing, to call out the cleanliness of the board, before I recieve it. These boards will require a tight spec after they are assembled, so I want to know that they are clean when I get them. Any suggestio

Solid Solder Deposit

Electronics Forum | Tue Aug 10 09:09:39 EDT 2004 | mattkehoe

wash->ssd top->wash->sticky flux bottom side->place smt components->reflow->wash->sticky flux top side->place topside smt components->reflow->wash) ssd is basically the process of applying solder paste to the pcb with a stencil and the solder reflowe

Re: uBGA Stencil Thickness

Electronics Forum | Mon Dec 21 17:50:55 EST 1998 | anamonus

| I have a mixed technology board ranging from 50 mil pitch devices to 20mil Qfp's to PBGA-352 at 1.27mm, and 6 Intel uBGA-48 at 30 mil pitch. With all these different package types i'm torn between using a 4 or 5mil thick stencil. The ball dia. is 1

Surfacemount Can Capacitors

Electronics Forum | Mon Apr 07 14:03:27 EDT 2003 | ksfacinelli

We have a client we would like to have switch from leaded can components to surface mount versions. We currently are utilizing these on a number of designs but his concern is in the area of reliability of the solder interface. The caps generally ha

Can excessive reflow(longer dwell time) cause open joint?

Electronics Forum | Thu Jul 29 00:42:32 EDT 2004 | C.W

hello, BGA was a little excessively reflowed with dwell time(above 183C - solder paste = 63/37) over 2 min, peak temp is 218C. I inspected the BGA under X-ray and there is a little voids but within the acceptable range, i then used the Ersascope to c

Re: Reflow Oven Evaluation Using Cpk

Electronics Forum | Sat Mar 21 12:10:03 EST 1998 | Philip C. Kazmierowicz

| Cpk's on top flight ovens (e.g., Conceptronics, Heller, Electrovert, Vitronics) vary wildly, from 1 to 2+, between different supplers. The suppliers don't seem to understand Cpk's. A supplier's rep whose oven has a Cpk of 1.0 told me: | 1. Cpk's

ICT and specifying PCBA testing

Electronics Forum | Tue Nov 01 14:46:31 EDT 2011 | davef

Agilent TestJet Technology White Paper In the early 1990s, the testing of digital parts became problematical. Previous in-circuit test techniques sought to ensure a correct, functioning part by applying digital patterns, called vectors, to the input

Pick and Place Startup - LQPF100 bridging issues

Electronics Forum | Thu Mar 25 20:50:50 EDT 2021 | stephendo

A couple more things. The PCB. What size are the pads? One time a board shop had difficulty putting masking between the pads of a QFP and the pads suffered as a result. When I told them they didn't have to have masking between the pads, the pads w

Component Packaging Trends

Electronics Forum | Thu Oct 15 14:35:44 EDT 1998 | Joseph Belmonte

Hi Folks, As I travel our industry it seems to me the trend is to move from finner and finner pitch QFP's to array packages (BGA's, CSP's, etc.). Do you folks see the same trend? What is the finest pitch QFP package you have used in your process? Are


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