Electronics Forum | Tue May 07 10:13:06 EDT 2019 | cyber_wolf
I have personally never seen a reflow profile change reduce voids. We have invited "experts" in to demonstrate this claim. They were unable to.
Electronics Forum | Mon May 27 04:36:08 EDT 2019 | SMTA-Rogers
Dear Sr.Tech, We tried to adjust the soak time and TAL time of reflow profile, but it doesn’t seem to help much.
Electronics Forum | Mon May 27 04:40:21 EDT 2019 | SMTA-Rogers
Dear Steve, We already to do some DOE of reflow profile, but the optimized parameters are not help for the reduction of voids.
Electronics Forum | Sat Jun 01 04:27:37 EDT 2019 | gregoryyork
Increase paste volume and use ramp soak spike profiling. Reducing volume of paste often leads to entrapment. Good idea to know difference between voiding and dewetting due to contamination
Electronics Forum | Mon Feb 06 17:58:16 EST 2023 | davef
The September 29, 2022 Express Newsletter [ https://smtnet.com/express/index.cfm?fuseaction=archives&issue=20220929 ] has papers on chip cracking
Electronics Forum | Wed Feb 08 09:43:08 EST 2023 | charles_nguyen
Thank you for the above information but what I want to talk about is the PCB design aspect. Should there be any warning about it in the DFM?
Electronics Forum | Thu May 09 08:36:18 EDT 2019 | solderkingchris
Hi, You can work on improving stencil design, having the perfect profile and other process improvements but it may be the paste itself letting you down. We have put a lot of work into developing our solder pastes to significantly reduce voiding. Y
Electronics Forum | Sun Apr 11 11:39:52 EDT 2010 | manchella
When we have sent some of motherboards for reliability testing in a tird party laoratory. It is found that when Dye&Pry is done after 600 cycles of Thermal Cycling, in LGA socket only one of the corner solder joing had 100% type 3 crack. All other so
Electronics Forum | Tue May 07 10:36:38 EDT 2019 | slthomas
Probably just means you started out with an optimal profile. I suspect that not everyone does. ;) It seems like we did have some luck with profile adjustments in one instance with some QFN's with a large thermal pad. Like I said, though, the profi
Electronics Forum | Thu May 30 09:33:15 EDT 2019 | emeto
Contributors in order of importance: 1. PCB design - if you have large thermal pads, a grid of via holes should be created. Components with low profile will not let the gas to escape from the joint. The only way is going down. 2. Reduce paste volum
