Electronics Forum | Tue Apr 03 22:03:18 EDT 2001 | davef
With friends like you, who needs enemies? I�d guess that the perceived benefits of flat pads for your 20 mil pitch and below components counter-balance the higher cost, gold being a solder pot contaminant, limited solder mask compatibility, potentia
Electronics Forum | Mon Apr 23 17:30:08 EDT 2001 | davef
Step 1: Print paste on the board, skip placement, reflow the board, check solderability. Step 2: Goto Step 1. White Tin Solderability: The most common reason for solderability issues with the white tin surface coating during multiple thermal excur
Electronics Forum | Tue May 29 16:52:07 EDT 2001 | hussman
By far the easiest way is to track solder paste measurement on your board - or solder defects after reflow (key word- easiest). Why spend 2 weeks examining a stencil when it clearly doesn't make defects, or IS making defects. I find using 2-D data
Electronics Forum | Fri May 11 15:43:41 EDT 2001 | davef
More information would be helpful. For instance: * Talk about the distribution of the problem, including a single lot or from various lots and over components and component types on the board * Tell us about the board (ie, thickness, type, solder ma
Electronics Forum | Mon Jun 18 17:41:07 EDT 2001 | genny
Hi, I put this on the technet forum, and I know some of the same people are here, but I thought I might catch others here as well. We have PCB's which are populated at the CM level with no-clean solder paste. However in house we use a solder wire s
Electronics Forum | Mon Jun 25 20:39:08 EDT 2001 | ianchan
Hi mate, no complete info given from what i see, so just some humble comments, mayhaps you review : 1) PCB pad finishing - Copper+nickle plated? coz if so, nickle is a KILLER to good solder wetting. what we did back here, was to HAL coat the nickle
Electronics Forum | Fri Jul 06 03:23:01 EDT 2001 | kennyhktan
Hi there Steven ! Please allow me to share some of my problem we're facing here with you. Here are a few points that I suggest you should check on your current process:- (1)PCB - Component land partern design ? It is per IPC spec ? - Mask
Electronics Forum | Fri Jul 06 18:19:41 EDT 2001 | davef
The senior staff have the pictures!!! Oh, that�s just GREAT!!! What the blank are these gerbils doing with �em? Nothin�!!! They�re probably sitting in a folder on whatzisname�s desk, until he has "a change to study them more". [Like he�s going t
Electronics Forum | Sat Jan 22 20:59:51 EST 2000 | Jeff Sanchez
Michael, I am not sure if you are trying to lay out a board with vias in the pads or suffer through an assembly you got stuck with? I am building run of boards right now that has vias in most the smt pads. I'm sure the design group thought it was
Electronics Forum | Fri Jan 14 07:55:07 EST 2000 | Pat Pepper
Hi Wolfgang, Thanks for the response. We had a similar situation to yours with some white tin samples that sat around for about eight months. Samples soldered right after they arrived soldered better than the ones we soldered eight months down the
