Electronics Forum | Mon Mar 27 20:59:41 EST 2000 | Dave F
Garo: Voids are primarily process indicators. There is experimental evidence that voids retard crack propagation locally around the void on a temporary basis. There is no standard, IPC or otherwise, on voids--nor should there be. See also J-STD-013,
Electronics Forum | Fri Mar 03 14:01:49 EST 2000 | dean
This technique is commonly known as "black boxing". The majority of IC's are marked with ink. Simply use a tiny piece of sandpaper to "scratch the surface" and render the device blank. This will work with Laser marked parts as well. If your volum
Electronics Forum | Thu Mar 02 09:13:07 EST 2000 | jacqueline Coia
Could anyone please tell me if there is a quick simple formula for working out the ideal SMD footprint for a 52 pin QFP using the dimensions specified on the manunfacturers component drawing. I know of the IPC 'SMD land patterns' standard, which I e
Electronics Forum | Mon Jan 22 09:06:21 EST 2001 | jmlasserre
Product concerned: Sdram memory. Due to the net resistor size and shape (0603, the lead of this component is very close to some vial hole. What is the minimum clearance we must have between a component lead and a pad or via ? For the pcb design th
Electronics Forum | Wed Jan 24 12:42:25 EST 2001 | traviss
I�m suddenly getting a very high failure rate in a TO99 component (National LM136AH-2.5). After some investigation we found some of these parts are more than 20 years old. What I am hoping for is that someone out there can help me find some standards
Electronics Forum | Thu Mar 01 16:58:05 EST 2001 | davef
Last time we looked at this, JEDEC carefully designated the dimensions of the carriers, but "neglected" to define the component orientation with the carrier. Go to http://www.jedec.org/download/, search for JEP95 JEDEC REGISTERED AND STANDARD OUTL
Electronics Forum | Tue Apr 10 12:56:23 EDT 2001 | slthomas
Didn't you hear? Fendelaz went out of business and sold the rights to the Magnaplancil to Amahlmahay. Sure, all the standard variables still affect the print quality (aka registration and volume) but if the machine controls everything but paste di
Electronics Forum | Tue Apr 17 21:30:27 EDT 2001 | davef
The issue is on the table. Which is it? Are you ... * Loosing your gold plate when you remove the tape? [A tape test is a standard test for evaluating gold fingers. Check IPC-TM-650, test number wachacallit. Checkitaut.] OR * Putting tape o
Electronics Forum | Sat Apr 14 03:34:23 EDT 2001 | kpliew
Hi Greg, If u don't mind my recommendations. U may want to try to convince them that by using smaller pad size , u save solder paste in the end of the day (provided u are doing mass volumes). It is another way of getting around to ur idea of changin
Electronics Forum | Mon Apr 16 12:59:51 EDT 2001 | Mike R
If you will place a temperature strip on the board during wave soldering process you will get a max of 210 F or 98.8 C which is normal on the standard wave temperature. The problem on the 10% solder on the TH via hole can be caused by insufficient fl
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