Electronics Forum | Wed Aug 25 16:42:32 EDT 1999 | Dave
| | | | | | Could use a little help here. Can anyone clarify to me the cause and fix of chip caps/resistors tombstoning following reflow? | | | | | | | | | | | | Any help would be appreciated. Thanks. | | | | | | | | | | | Most common reason is
Electronics Forum | Wed Aug 25 21:44:03 EDT 1999 | Jason Tomlinson
| | | | | | Could use a little help here. Can anyone clarify to me the cause and fix of chip caps/resistors tombstoning following reflow? | | | | | | | | | | | | Any help would be appreciated. Thanks. | | | | | | | | | | | Most common reason is
Electronics Forum | Mon Aug 23 11:27:00 EDT 1999 | Dave F
0.6 �m (25 micro inches) and self-limit around 5 mils depending on the material being plated and the process. Similarly with white tin, laminates with cleaned copper are immersed in a series of tin baths without an external source of electric curren
Electronics Forum | Wed Aug 18 16:15:04 EDT 1999 | Earl Moon
| Hadco offers a technology of building in a "buried" capacitance layer (& other embedded passives) in organic PWBs (FR4 for example). see http://www.hadco.com/prod03.htm and a design manual is posted here: http://www.hadco.com/pdfs/bcguide.pdf | I
Electronics Forum | Sat Aug 14 07:01:44 EDT 1999 | Earl Moon
| Has anybody adopted the method of stencil printing with the board at a 45 degree angle to the squeegee blade? What are the benefits and drawbacks? I've heard you get better fine pitch results. | | TX | Mark | I know we all seek easy/better solut
Electronics Forum | Tue Aug 10 07:47:12 EDT 1999 | Brian
| | | hello to everybody, | | | we have a really satisfactory no clean process, both smt/reflow and wave soldering, but we get troubles with defects rework; | | | does anybody know how to eliminate flux residues or how not to produce them during rew
Electronics Forum | Tue Aug 10 20:22:15 EDT 1999 | Wayne Sanita
Hello, Could be that touchup operators are using too much flux. What are you dispensing flux with. Disposable or refillable flux pens are good to have around. | | | | hello to everybody, | | | | we have a really satisfactory no clean proc
Electronics Forum | Tue Aug 03 13:03:20 EDT 1999 | Dave F
| | I have been asked to supply a maximum shelf life for our assemblied PCB's. I realise this is dependent on so many factors- temperature, humidity, no of layers etc. But does anyone have a formulae for calculating shelf life, or does anyone know of
Electronics Forum | Tue Aug 03 13:03:48 EDT 1999 | Dave F
| | I have been asked to supply a maximum shelf life for our assemblied PCB's. I realise this is dependent on so many factors- temperature, humidity, no of layers etc. But does anyone have a formulae for calculating shelf life, or does anyone know of
Electronics Forum | Wed Jul 28 20:56:58 EDT 1999 | Dave F
| Currently, we are baking any PCB before process on SMT, the 'reason' is to dry any possible humidity that could be inner the PCB, it does not matter if the PCB is multilayer or not. We bake PCB's at 107C for 4 hrs and the board must be process into
