Electronics Forum | Fri Mar 03 14:40:22 EST 2006 | amol_kane
i think a more important issue here would be the reduction ratio. as LF solders have a higher surface tension, they do not flow as well as their leaded counterparts. therefore the stencil design may have to be changed (hence a new stencil) if the red
Electronics Forum | Wed Oct 11 13:39:49 EDT 2006 | russ
Dissipative flooring is not really "conductive" so to speak. what it does is (supposedly)dissipate charge as it accumulates on the surface of mat. Does this mat have a ground lug on it? Responses are correct, unless you can get conductivity between
Electronics Forum | Thu Jul 22 17:39:58 EDT 2021 | proceng1
We do use a company for custom fixtures, but we also make some in house. The biggest hurdle for a board that requires a fixture to go through printing and SMT is that the board has to be the tallest thing. So any hold downs or locating hardware has
Electronics Forum | Sun Mar 01 15:52:13 EST 1998 | Earl Moon
| From several months I am investigation about the VOIDS PERSENCE and his important as reliability. | One question now is : | It is possible that on the BGA components the voids are already present into the balls, before the mounting on the pcb ? | I
Electronics Forum | Tue May 26 14:39:40 EDT 2009 | boloxis
QFN or MLFs are mainstream now, QFNs already evloved to much more complex versions now like matrix pins, stacked dice and flipchip versions. IPC 610D already includes them, just make sure the pins have solder plating, the PWB pads have soldermask in
Electronics Forum | Sat Oct 24 06:07:09 EDT 1998 | Earl Moon
| Hi, | Am looking out for companies which would perform the "highly accelerated stress testing" for my PCB test assembly samples. does anybody have any info regarding this. | thanks, | subhash | Most independent PCB test labs, often doing military
Electronics Forum | Mon Oct 26 14:56:07 EST 1998 | carl m
| | Hi, | | Am looking out for companies which would perform the "highly accelerated stress testing" for my PCB test assembly samples. does anybody have any info regarding this. | | thanks, | | subhash | | | Most independent PCB test labs, often do
Electronics Forum | Fri Jun 23 10:10:15 EDT 2006 | Gman
Some amount of voiding was always seen on sites where solder paste is printed. These voids are much smaller. However the site where a flip chip is flux dipped has never had problems with voiding. Macro voids (and huge ones at that)across the board s
Electronics Forum | Tue Nov 28 21:16:17 EST 2006 | davef
J Rose at EMPF says: The introduction of no-clean solder fluxes in electronics manufacturing has given rise to greater levels of solder balling simply because the opportunity to remove them in the wash process does not exist. They are typically cause
Electronics Forum | Wed Aug 21 17:44:32 EDT 2002 | davef
Splitting hairs, I expect SIR of all solderability protection, including OSP, to decrease after reflow. What�s more, I expect the SIR of all solderability protection to pretty much decrease over time. The �comb pattern� test specimens meet requirem
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