Electronics Forum: systematic (Page 1 of 1)

Re: CPk

Electronics Forum | Thu Dec 09 15:03:39 EST 1999 | Andy Yates

I would suggest that as well as repeatedly inspecting the same board and looking at the standard deviations of the measurements, you should perform some form of accuracy test either by measuring a known glass plate or by inspecting a board at 0 and 1

Library with SMT Components

Electronics Forum | Wed Oct 13 05:46:27 EDT 2004 | apetkov

Hi Do you know about some kind of database (library) with physical specifications of the most widely distributed SMD Components. Something like BGA, QFP, SOP, etc. and for each corpus width, length, pins, etc. JEDEC has something similar, but t

Re: Slim-Kic prophet system

Electronics Forum | Wed May 27 15:50:04 EDT 1998 | Rick

The KIC Prophet system does indeed deliver as promised. The Slim-KIC (datalogger portion) works well and is worth the price of admission by itself. The Prophet portion of the system (resident in the oven) works great and decreases the requirement for

Reflow profile basics

Electronics Forum | Sat May 08 07:50:24 EDT 2004 | snehal acharya

pls can any body throw some light on the reflow profiling? what r the basic requirements of thermal profiling? how we can achive better profiling? what is the need of doing profiling? what precaution should one take while doing profiling? profile is

Tombstone

Electronics Forum | Tue Aug 28 13:08:28 EDT 2001 | seand

Hello Everyone, Mountains and mountains of data in the archives. As a contractor the variables in your production lots don't help I'm sure. On a larger scale, one suggestion maybe to first look at when and where your tomb stoning is occuring. 1

Re: ESD....I don't wanna shock anyone, but...

Electronics Forum | Wed Jun 02 15:54:26 EDT 1999 | Dave F

| ok, ok, so I'm not an engineer. I'm a salesguy ( and that's nothing to be ashamed of...) Here's my dilemma. I represent a contract manufacturer who is in the early stages of quoting on "turnkey" assembling of a circuit board for a manufacturer

Re: ESD....I don't wanna shock anyone, but...

Electronics Forum | Thu Jun 03 12:37:16 EDT 1999 | John Thorup

| | ok, ok, so I'm not an engineer. I'm a salesguy ( and that's nothing to be ashamed of...) Here's my dilemma. I represent a contract manufacturer who is in the early stages of quoting on "turnkey" assembling of a circuit board for a manufacture

pbga substrate crack vision system

Electronics Forum | Thu Sep 24 18:57:03 EDT 2009 | davef

From "siliconfareast.com": Basic Die Cracking FA Flow 1) Failure Information/Device and Lot History Review. Understand the customer's description of the failure, i.e., the failure mode, where it was encountered, what conditions the sample was subject

Re: More informations on water clean for CSP/BGA package

Electronics Forum | Wed Oct 06 03:58:25 EDT 1999 | Brian

| | Hi, | | | | Help! Could anyone help to enlighten me on this? | | | | Question: | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z that using a n

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