Electronics Forum: vias (Page 1 of 162)

Cracked vias

Electronics Forum | Sun Dec 15 22:31:43 EST 2002 | craigj

Has anyone heard of vias cracking (barrel from pad) when being wave soldered. Was told this was a big problem by contract pcb designer, he always tent vias because of this. The reason was that the solder filling the vias caused stressing and then sep

BGA vias

Electronics Forum | Sat Aug 28 11:03:44 EDT 2004 | mariels

We are currently designing a multi-layer board using a BGA with a pitch of 1mm. Need to find out what hole/pad size via and if they should be plated holes? Thanks

BGA vias

Electronics Forum | Tue Aug 31 15:47:24 EDT 2004 | davef

Choices are: * Via Pad / Drill = 0.020 / 0.010 (Inches) * What ever the IPC land calculator says

Cracked vias

Electronics Forum | Mon Dec 16 09:36:54 EST 2002 | russ

I have never had this problem. It sounds like you are right in imagining that there must have been a bad supplier of PCBS or an inadequate design rule being followed, or a very bad wave process to have this cracking over wave solder. Some books requ

Cracked vias

Electronics Forum | Mon Dec 16 10:54:48 EST 2002 | davef

Knee of barrel and pad crack: Caused by thermal stress during soldering, because epoxy expands in the "z" 3X more than "x" or "y" which are restricted by the fiber. Related to: * Design of pads too large relative to hole diameter * Temperature at o

Design rule for vias

Electronics Forum | Tue Dec 05 21:36:51 EST 2006 | Jimmy

Hello, Currently, we are running new product,server card, and encountered hugh false alarm (17%) at ICT station. Already confirm its is not flux issue...False call always on the vias location. I also notice the vias size is much smaller than those

Tenting of vias

Electronics Forum | Tue Aug 18 10:18:22 EDT 1998 | Dave Hulbert

I have a question on tenting of vias on PWB's. I have designed a 6 >layer, military, mixed components (all on top side), LPI soldermask >board which will be run over the wave. I was planning on tenting vias >but did not specifically specify that on f

Re: Tenting of vias

Electronics Forum | Mon Aug 31 14:03:41 EDT 1998 | Bill Childs

I have a question on tenting of vias on PWB's. I have designed a 6 >layer, military, mixed components (all on top side), LPI soldermask >board which will be run over the wave. I was planning on tenting vias >but did not specifically specify tha

Design rule for vias

Electronics Forum | Wed Dec 06 21:28:12 EST 2006 | davef

It's worse than just using the test equipment manufacturer guidelines. Along with that, you have to deal with each of the test fixture fabricators' preferences as well. What this boils down to is a negotiation with the test engineering group as to w

Tented vias on ENIG boards

Electronics Forum | Wed Feb 01 18:11:43 EST 2006 | Chris

I wonder if they are concerned about getting chemicals trapped in the tented vias. If the tented vias have pin hole openings or even larger openings, chemicals from the ENIG process could become entrapped in the via holes and not washed away in the

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