Electronics Forum | Sat Oct 19 11:48:39 EDT 2002 | davef
Good points, John. Continuing to track on the voiding issue, why remove voids anyhow? * Voids are primarily process indicators. There is experimental evidence that voids retard crack propagation locally around the void on at least on a temporary bas
Electronics Forum | Tue Mar 09 17:52:05 EST 2004 | davef
Bryan: Comments are: * You're correct, solder paste formualtion is a major driver to voiding in BGA balls. * Voids are primarily process indicators. There is experimental evidence that voids retard crack propagation locally around the void on a temp
Electronics Forum | Mon Sep 17 19:33:27 EDT 2007 | davef
We have never studied this, but here's what we'd guess. If there are void in BGA solder balls at inbound: * A proper reflow recipe will eliminate the void. * A poor recipe will allow the void to remain and possibly generate additional void.
Electronics Forum | Thu Sep 06 11:06:11 EDT 2007 | tphan
Can voids be carried over from original voids in solder balls during reflow?
Electronics Forum | Mon Mar 27 20:59:41 EST 2000 | Dave F
Garo: Voids are primarily process indicators. There is experimental evidence that voids retard crack propagation locally around the void on a temporary basis. There is no standard, IPC or otherwise, on voids--nor should there be. See also J-STD-013,
Electronics Forum | Mon Jan 13 18:22:55 EST 2003 | davef
100 sec) and decrease reflow temp to 205C. * Understand that voids are primarily process indicators. There is experimental evidence that voids retard crack propagation locally around the void on a temporary basis. There is no standard, IPC or otherw
Electronics Forum | Thu Apr 23 15:46:08 EDT 2009 | ccross
During initial profiling we shoot for 15% or less voiding on our BGAs. During production runs we consider voids under 15% to be ok. Voiding between 15%-25% we string tag and pay more attention to during test. Over 25% we consider a reject.
Electronics Forum | Mon Jun 24 22:39:25 EDT 2019 | sssamw
yes, the void should not expose the conductor or bridge the conductor, the coating there should be thick as IPC required but you need minimize the voids and bubbles. ALso for those small chips, a void or bubble on it means possible ECM, normlly shou
Electronics Forum | Tue Nov 26 09:07:16 EST 2019 | scotceltic
I am more worried about those voids also instead of the voids in the thermal pads. I still can't find any IPC spec that calls out a min. void percentage other than on BGA packages.
Electronics Forum | Mon Jan 17 18:36:26 EST 2000 | William
Voids can be acceptable @ 24% per 5 balls area, and 8% per single ball area. In fact, Proceeding Book 1996; Vol. I, Page #126 conclusions saids: that solder joint voiding at the maximun levels pbserved in this study (were voided area was up to 24 per
