Minimizing Voiding In QFN Packages Using Solder Preforms
Published: |
July 27, 2012 |
Author: |
Seth J. Homer, Ronald C. Lasky, PhD, PE |
Abstract: |
First published in the 2012 IPC APEX EXPO technical conference proceedings. The focus of this paper will quantify the preform requirements and process adjustments needed to use preforms in a standard SMT process. In addition, experimental data showing vo... |
|
|
|
|
|
|
You must be a More articles from Indium Corporation »
- Jan 03, 2021 - Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP and Flip Chip Technologies
- Dec 29, 2020 - D-PAK Voiding: A Study to Determine the Origins of D-PAK Voiding
- Nov 24, 2020 - The Risk And Solution For No-Clean Flux Not Fully Dried Under Component Terminations the Risk And Solution For No-Clean Flux Not Fully Dried Under Component Terminations
- Jul 24, 2019 - Voiding Performance with Solder Pastes Containing Modified SAC Alloys for Automotive Applications in Bottom Terminated Component Assemblies
- Dec 19, 2018 - Process Optimization for Fine Feature Solder Paste Dispensing
- See all SMT / PCB technical articles from Indium Corporation »
More SMT / PCB assembly technical articles »
- Dec 07, 2020 - A Non-destructive Approach to Identify Intermittent Failure Locations on Printed Circuit Cards (PCC) that have been Temperature Cycle Tested | ACI Technologies, Inc.
- Dec 02, 2020 - SMT007-MIRTEC Intelligent Factory Automation Article-November 2020 | MIRTEC Corp
- Nov 09, 2020 - Ball Grid Array (BGA) Voiding Affecting Functionality | ACI Technologies, Inc.
- Nov 04, 2020 - Higher Defluxing Temperature and Low Standoff Component Cleaning - A Connection? | ZESTRON Americas
- Sep 02, 2020 - Reworking ALD Coatings | ACI Technologies, Inc.
- Browse Technical Library »
Minimizing Voiding In QFN Packages Using Solder Preforms article has been viewed 492 times
