Assembly Reliability of TSOP/DFN PoP Stack Package

Published:

December 12, 2018

Author:

Reza Ghaffarian, Ph.D.

Abstract:

Numerous 3D stack packaging technologies have been implemented by industry for use in microelectronics memory applications. This paper presents a reliability evaluation of a particular package-on-package (PoP) that offers a reduction in overall PCB board area requirements while allowing for increases in functionality. It utilizes standard, readily available device packaging methods in which high-density packaging is achieved by: (1) using standard "packaged" memory devices, (2) using standard 3-dimensional (3-D) interconnect assembly. The stacking approach provides a high level of functional integration in well-established and already functionally tested packages. The stack packages are built from TSOP packages with 48 leads, stacked either 2-high or 4-high, and integrated into a single dual-flat-no-lead (DFN) package....

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Company Information:

Jet Propulsion Laboratory

The JPL is the lead U.S. center for robotic exploration of the solar system, and conducts major programs in space-based Earth sciences and astronomy.

Pasadena, California, USA

IPC Standards Certification Center, Training Provider

  • Phone +1-818-354-4321

Jet Propulsion Laboratory website

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