Redundancy Yield Model for SRAMS
Published: |
May 7, 1999 |
Author: |
Nermine H. Ramadan, STTD Integration/Yield, Hillsboro, OR, Intel Corp. |
Abstract: |
This paper describes a model developed to calculate number of redundant good die per wafer. A block redundancy scheme is used here, where the entire defective memory subarray is replaced by a redundant element. A formula is derived to calculate the amount of improvement expected after redundancy. This improvement is given in terms of the ratio of the overall good die per wafer to the original good die per wafer after considering some key factors.... |
|
|
|
|
|
|
You must be a Company Information:
More articles from Intel Corporation »
- Dec 16, 2021 - Package-on-Package (PoP) Warpage Characteristic and Requirement
- Jan 06, 2021 - Challenges of Manufacturing with Printed Circuit Board Cavities
- Dec 12, 2019 - Voids in Solder Joints
- Oct 08, 2015 - Preparing for Increased Electrostatic Discharge Device Sensitivity
- Apr 16, 2015 - Stereo Vision Based Automated Solder Ball Height Detection
- See all SMT / PCB technical articles from Intel Corporation »
More SMT / PCB assembly technical articles »
- Mar 19, 2024 - What is Underfill | GPD Global
- Mar 19, 2024 - Made in Japan: Solder Paste Jet Dispensing Machine | I.C.T ( Dongguan ICT Technology Co., Ltd. )
- Feb 26, 2024 - Precision Control in Electronic Assembly: Selective Wave Soldering Machine | I.C.T ( Dongguan ICT Technology Co., Ltd. )
- Feb 02, 2024 - Maximizing Efficiency: The High-Speed SMT Line With Laser Depanelizer | I.C.T ( Dongguan ICT Technology Co., Ltd. )
- Dec 27, 2023 - Revolutionizing Tech: SMT Auto IC Programming Machine Mastery | I.C.T ( Dongguan ICT Technology Co., Ltd. )
- Browse Technical Library »
Redundancy Yield Model for SRAMS article has been viewed 535 times
