Component Failure Analysis - Hermetic Packaging
Published: |
June 11, 2019 |
Author: |
ACI Technologies, Inc. |
Abstract: |
Recently ACI Technologies was asked to perform failure analysis on a hermetically sealed transistor for potential electrostatic discharge (ESD) or electrostatic overstress (EOS). ACI was asked to determine if the field-failed transistor was damaged by ESD or EOS. In order to properly assess the failure, additional samples were requested.... |
|
|
|
|
|
|
You must be a Company Information:
More articles from ACI Technologies, Inc. »
- Dec 07, 2020 - A Non-destructive Approach to Identify Intermittent Failure Locations on Printed Circuit Cards (PCC) that have been Temperature Cycle Tested
- Nov 09, 2020 - Ball Grid Array (BGA) Voiding Affecting Functionality
- Sep 02, 2020 - Reworking ALD Coatings
- Aug 05, 2020 - ALD of Alumina Ceramic Films for Hermetic Protection
- Jul 01, 2020 - Lead-Free Risk Mitigation -- A Case Study
- See all SMT / PCB technical articles from ACI Technologies, Inc. »
More SMT / PCB assembly technical articles »
- Mar 19, 2024 - What is Underfill | GPD Global
- Mar 19, 2024 - Made in Japan: Solder Paste Jet Dispensing Machine | I.C.T ( Dongguan ICT Technology Co., Ltd. )
- Feb 26, 2024 - Precision Control in Electronic Assembly: Selective Wave Soldering Machine | I.C.T ( Dongguan ICT Technology Co., Ltd. )
- Feb 02, 2024 - Maximizing Efficiency: The High-Speed SMT Line With Laser Depanelizer | I.C.T ( Dongguan ICT Technology Co., Ltd. )
- Dec 27, 2023 - Revolutionizing Tech: SMT Auto IC Programming Machine Mastery | I.C.T ( Dongguan ICT Technology Co., Ltd. )
- Browse Technical Library »
Component Failure Analysis - Hermetic Packaging article has been viewed 591 times
