For the first time, a paper detailing Motorola's HiPerMOS 8 (or ``HiP8'') 0.10 micron CMOS (complementary metal oxide semiconductor) platform technology is being presented at the meeting. The HiP8 technology realizes a 30 percent reduction in line width over the current HiP7 0.13 micron generation. This shrink is engineered to enable a 50 percent reduction in chip size by increasing gate density and reducing SRAM bitcell area, while enhancing performance. The increased density and functionality is expected to spawn a wide range of new products for networking, computing, embedded processing, and wireless and transportation applications. For example, the consumer wireless arena can expect to realize a decisive advantage in customer value for such applications as 3G handheld devices.
This high performance, low power technology is expected to be manufactured using Motorola's fourth generation of copper interconnect. Designed as a true platform technology, HiP8 supports dual/triple gate oxide, analog, and non-volatile memory modules. The technology is designed with the flexibility to support a broad range of low power, high performance and silicon on insulator (SOI) applications. In addition, the HiP8 platform is ``foundry compatible'' with respect to design rules and electrical targets, and is capable of easily supporting third party designs and libraries. The HiP8 technology is expected to complete process certification in December 2002.
``This HiP8 platform technology shows our continuing commitment to rolling out advanced technologies to transform the way people live, work and play. We are focused on building technologies that enable system on chip solutions across a wide range of applications,'' said Dr. Louis C. Parrillo, corporate vice president and chief technology officer of the Semiconductor Products Sector for Motorola. ``This CMOS platform technology, combined with our capability to integrate our own breadth of advanced modules, forms the foundation of Motorola's embedded leadership. Looking out even further, Motorola is exploring materials that will meet industry needs for generations to come.''
Future generations of CMOS technology will require replacement of the silicon dioxide gate dielectric with a material having a substantially higher dielectric constant (a ``high-k'' material) to suppress leakage through the gate dielectric. Motorola's development of a high-k material is being highlighted in a paper describing the integration of a hafnium oxide gate dielectric into a standard CMOS process. Current leakage is reduced by a factor of 1000 by switching from silicon dioxide to hafnium oxide. This achievement will help enable further shrinking of CMOS devices allowing for continued increases in device density. It will also help to improve device performance while minimizing power consumption.
Additional technology highlights being presented at IEDM by Motorola's semiconductor technology laboratories include:
- A short course on non-volatile Magnetoresistive Random Access Memory
- A short course on high-k gate dielectric and metal gate for sub-70 nm
CMOS. An innovative mechanism of hot carrier degradation in highly
scaled CMOS devices
- Novel direct tunneling current method of channel length extraction
- A comprehensive study of substrate noise isolation for mixed signal
As the world's #1 producer of embedded processors, Motorola's Semiconductor Products Sector creates DigitalDNA system-on-chip solutions for a connected world. Our strong focus on communications and networking enables customers to develop smarter, simpler, safer and synchronized products for the person, work team, home and automobile. Motorola's worldwide semiconductor sales were $7.9 billion (USD) in 2000. http://www.motorola.com/semiconductors/
Motorola, Inc. (NYSE: MOT - news) is a global leader in providing integrated communications solutions and embedded electronic solutions. Sales in 2000 were $37.6 billion (USD). http://www.motorola.com/
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