Electronics Forum | Thu Jan 09 15:19:41 EST 2014 | davef
For a typical wear surface application [millions of wipes], I agree with hege. You need to be talking electrolytic gold, NOT immersion gold. IPC-2221 says something like ... For edge connectors and areas not to be soldered: * Nickel - 2.5um [~100uin]
Electronics Forum | Wed Oct 24 18:09:44 EDT 2001 | davef
Allowing the board fabricator to define the board you expect to receive is fine, as long as they do a good job. Regardless of the existence of a clear product definition or not, it�s reasonable for you to argue that your receipts must meet the requi
Electronics Forum | Wed Jan 09 12:20:00 EST 2002 | mregalia
Thanks for cluing me into IPC-2221. Though the numbers they give seem to contradict what I have learned from people working with the materials. At least I now know where the guideline for a max of 30 microinches of gold for soldering comes from. But
Electronics Forum | Tue May 28 21:00:59 EDT 2002 | davef
That is the rub here, isn�t it? For those posting, it�s easier [but much slower] to start a new thread than to search the archives. [And posters could view their issue so unique and novel that it could never have been discussed several years earlie
Electronics Forum | Fri Nov 25 15:52:40 EST 2011 | davef
"IPC-2221 - Generic Standard On Printed Board Design" talks to fiducials. Anther take on fiducials says they shall meet the following requirements. * Make fiducials 1 - 1.5 mm diameter circle. * Cover fiducials with tin. * Keep solder mask opening at
Electronics Forum | Mon Dec 13 00:48:33 EST 1999 | armin
Hi All I have a 0.7 mm diameter hole for vias, what�s the minimum annular ring for this hole diameter? What�s the term unsupported and supported holes refer to in IPC-2221 9.1.2 Annular Ring Requirements? I have a proto-type PCB (designed by our R&
Electronics Forum | Mon Sep 20 13:04:25 EDT 2004 | davef
The Intel BGA Developer�s Guide [ http://developer.intel.com/design/packtech/ch_14.pdf ] says: 14.8.3.3 Plated Through Hole (PTH) Isolation Regardless of the technique used for the mounting pads shape or definition, isolation of the plated through h
Electronics Forum | Tue Dec 14 22:17:33 EST 1999 | Dave F
Armin: How ya doin� bud? CK gives good advice, but I'd like to take a bit of a different angle. Q1. For 0.7 mm (0.027in) diameter hole for vias, what�s the minimum annular ring for this hole diameter? Depends on what you�re trying to do. For in
Electronics Forum | Thu Nov 19 08:20:04 EST 1998 | Earl Moon
| | | | For some as yet unkown reason, we have started to have some boards sag and go under the wave. The boards are surface mount top side and conventional components wave soldered. We have checked the wave hight and both the profiles on the wave so
Electronics Forum | Thu Nov 19 09:01:00 EST 1998 | Dave F
| | | | | For some as yet unkown reason, we have started to have some boards sag and go under the wave. The boards are surface mount top side and conventional components wave soldered. We have checked the wave hight and both the profiles on the wave
