Electronics Forum | Wed Jan 17 08:27:38 EST 2007 | Bob R.
Is there a standard (IPC, JEDEC, JEITA, etc) covering the tolerances on percentages of Sn, Ag, and Cu in SAC305? I'd also be interested if there are standard allowable amounts of other contaminants. I couldn't turn up anything in a search of the IP
Electronics Forum | Thu May 31 12:21:14 EDT 2007 | patrickbruneel
Let me give you some good advice You take already plenty of risk going lead-free, DO NOT use halogen containing fluxes in a lead-free no-clean process. Halogens left on the board will convert tin, silver and exposed copper into metal salts over tim
Electronics Forum | Fri Nov 05 10:59:30 EDT 2010 | methos1979
I have had my system for three weeks now. It is an MV3L. It is running version 4.5.0 build 2.1.2 software and it is very stable. I have not had a single crash. We are not a board manufacturer but rather use our system to inspect both populated an
Electronics Forum | Thu Apr 07 10:58:01 EDT 2005 | Dhanish
Need help from the experts on 1)simple way to measure the PCB warpage 2)what is the maximum warpage can the SMT machine allow the to accept and place the component without problem. 3)I have seen some people are using 7mils/inch as a Warpage spec. a
Electronics Forum | Fri May 15 10:04:59 EDT 2009 | aj
Hi all, Is there any standard for percentage voiding on the center thermal pad on a QFN? We use the dot matrix array for paste to allow for outgassing etc, but we have had a couple of xray inspection "fails" for voiding on this pad , in or around 3
Electronics Forum | Thu Oct 26 16:38:08 EDT 2000 | Philip A. Reyes
Hi Sir Charles! Good Day! I hope you can help me about my queries. 1. What is the acceptable misregistration or misalignment of balls after reflow soldering of PBGA module on the PCB? 2. Is there any criteria for solder ball defect or solder beads
Electronics Forum | Wed Feb 02 21:56:11 EST 2005 | davef
Based on X-ray imaging, IPC-7095 standard specifies three categories for void size for BGA solder joints. These categories are based on the percentage of joint cross sectional area occupied by the voided area. Class III Small: Void area is LT 9% Cla
Electronics Forum | Mon Dec 06 13:32:47 EST 1999 | Bob Smith
CPk is a measure of the process variance with respect to the acceptable upper and lower limits. In your case it would be the accuracy of placement. The exact position of a chip ideally would be dead centre on the pads however in real life that positi
Electronics Forum | Thu Apr 07 20:16:23 EDT 2005 | davef
Q1) Simple way to measure the PCB warpage A1) IPC-TM-650; Method 2.4.22 Bow & Twist Q2) What is the maximum warpage can the SMT machine allow the to accept and place the component without problem. A2) That depends. IPC-A-610 Acceptability of Elect
Electronics Forum | Sat Nov 18 21:20:58 EST 2006 | Fer
Dave, May I ask where did you find the 1.5%, or the goal of .005" (or .007") per inch? The IPC-A-600 bow and twist standard calls for a .75% based on the calculation of the test method TM-650, method 2.4.22, which calculates the percentage based on
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