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PCB Au thickness

Electronics Forum | Tue Oct 07 08:38:05 EDT 2003 | davef

J-STD-001C requires removal of gold from (through-hole) component leads when the thickness of the gold layer is above 2.5 microns to prevent problems with embrittlement. The thickness of gold on an ENIG board typically is around 0.05 micron, resultin

PTH Voiding Caused by Gold Plated Leads

Electronics Forum | Tue May 21 16:18:57 EDT 2019 | edhare

Interesting problem. I've seen this before on SMT device leads (see Gold Embrittlement paper at http://www.semlab.com). The AuSn4 IMC is solid at typical reflow temperatures and traps volatiles in the solder joint. One usually cannot crank the ref

Re: Noclean soldering to gold

Electronics Forum | Tue Dec 07 08:11:04 EST 1999 | Wolfgang Busko

Hi Russ, there�s something I don�t understand about the measures you took. I guess that TAL means time above liquidous and shortening of that time can result in bad dissolution of the protective Au-layer. The necessary time for the Au to mix with you

PCB Gold Plating

Electronics Forum | Fri Feb 09 20:05:15 EST 2001 | benefid

The ENIG process will yield between 3-7 micro inches (110 - 275 microns) of gold over the nickel barrier. This thickness range is pretty much the limit as this is a self limiting displacement reaction process. Once all surface nickel ions are repl

Gold Leaded SMT devices

Electronics Forum | Tue Sep 09 20:32:10 EDT 2003 | davef

The maximum ratio of gold weight to solder alloy weight can be calculated, to help prevent a problem from excessive gold-tin intermetallic compound (i.e., AuSn4). For the equation and its derivation, please refer to "The Use of Capillary Action Measu

Re: Dark Pad / Gold Embrittlement?

Electronics Forum | Thu Jul 27 21:57:16 EDT 2000 | Dave F

Hi Doug: Responding to your questions: � If gold over nickel is self limiting ... You didn�t say whether you gold plating was electroless or immersion. Electroless is not is self limiting. It can plate up to 5 thou. Expect immersion plated gold to

Re: Time to use alternative finishing ???

Electronics Forum | Mon Sep 13 06:23:06 EDT 1999 | Earl Moon

| | We have a product, with various PWBs, with over 600 parts each one (We are a low Volume/high mix company with an average component placement per PCB between 250 to 300 parts). This PWBs have 7 to 10, 20 mils pitch parts. We are having problems wi

Substrate Au/Ni thickness

Electronics Forum | Thu Feb 15 19:41:38 EST 2001 | davef

What do you mean by "But after performing temperature cycle test, the former aging rate (from the shear strength ) seems faster than the latter."? Comments are: I can't recall having heard the term "precipitation hardness" [not that that means anyt

Re: Tinning gold plated leads ( DIP, etc)

Electronics Forum | Tue Mar 21 20:25:30 EST 2000 | Dave F

John: What�s the matter? Free gold � good thing for you, bad thing for your supplier. :^) Pre-tinning of gold plated leads is important to: � Prevent gold embrittlement of the solder joint � Determine if the leads are solderable prior to assembly (


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