Electronics Forum | Thu Mar 24 16:06:34 EDT 2011 | nkinar
Thanks for the reply, davef. Due to prototyping time constraints, I've been asked by the engineers if I could do something on the SMT line to salvage this prototype PCB. Could I do anything to connect the pad or fill the via? Much of the board h
Electronics Forum | Thu Aug 16 04:35:10 EDT 2012 | craigweir
Can anyone advise on the risks involved in using a (previously soldered) component, in this case an 'SOIC8', as pick-up area for subsequent pick/place operation of sub-assy to larger motherboard ? The sub-assy in question would be a small outline(25
Electronics Forum | Tue Oct 16 11:02:05 EDT 2012 | terry_zhang
Has anyone tried to immerge the PCBA(with ICs, resistors, capacitors,connectors populated) into IPA for 1hr? The temperature of IPA is about 60~70C, is there any damage or degrating found for PCB and the components? Is there any related information s
Electronics Forum | Thu Feb 21 11:22:06 EST 2013 | emeto
It is a very interesting thought. However, teach all positions on the PCB might be challenging if you don't have them in the file. I think it is a smart think for OEMs as they would have all the resources to control their files. For CEM I don't see i
Electronics Forum | Thu Aug 01 00:17:17 EDT 2013 | paul_bmc
SMTnet colleagues, I am looking for your opinions on the PCB/CCA cleaning process. Regardless of fluxes or population complexity I want your opinion on these three cleaning processes and what you consider to be the best for what and why. Thanks for
Electronics Forum | Thu Aug 01 00:17:28 EDT 2013 | paul_bmc
SMTnet colleagues, I am looking for your opinions on the PCB/CCA cleaning process. Regardless of fluxes or population complexity I want your opinion on these three cleaning processes and what you consider to be the best for what and why. Thanks for
Electronics Forum | Wed Jan 25 00:29:22 EST 2017 | cmarasigan
This is our practice already, common profile both sides and we perform it during NPI stage. As long as zone settings are the same and profile requirements are meet, we consider it as same profile and no need to re-profile from bottom side process to
Electronics Forum | Tue May 02 15:25:22 EDT 2017 | mrk
Hi, We have recently been tasked with producing a PCB assembly that requires a chip resistor to be stacked on top of a chip capacitor (both are 0603 package size). This becoming a more common practice, I was wondering if anyone has been successful i
Electronics Forum | Fri Feb 28 08:48:00 EST 2020 | SMTA-Joe
We've made the decision to move towards Gold Immersion on our PCBs to eliminate flatness issues with QFNs and BGAs. Land/component pad geometry, population density, and other factors, have made it necessary to ensure a near perfectly flat surface tha
Electronics Forum | Mon Jan 09 11:34:40 EST 2023 | tommy_magyar
How big is the board? What is the thickness? How populated is it? Is it warping in the reflow oven? If yes, does the oven have any support? How big is the pad compared to the component footprint? How thick is the stencil? Are the components checked b
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