Electronics Forum | Tue May 11 06:30:41 EDT 1999 | Joe Byrde
| | | | | | | | | | | I left the company before this thing ever got resolved, so I don't know the answer, but here's what we did to get boards out the door. Baked them in a desicating oven. You know, the kind that pulls vacuum? It was a regular
Electronics Forum | Mon May 10 13:35:14 EDT 1999 | Chrys Shea
| We have been having an ongoing problems with radial electrolytic capacitors (thru hole)for some time. | 1. When we wash them in our inline cleaners the sleeving shrinks up from the PCB leaving the 'can' exposed. Some designs have traces on the
Electronics Forum | Mon May 10 14:44:15 EDT 1999 | C.K.
| | We have been having an ongoing problems with radial electrolytic capacitors (thru hole)for some time. | | 1. When we wash them in our inline cleaners the sleeving shrinks up from the PCB leaving the 'can' exposed. Some designs have traces on
Electronics Forum | Wed Mar 24 16:54:38 EDT 2010 | stepheniii
J-STD-033B.1 Says "For cavity packages in which water may be entrpped, water clean processes after first reflow can be an additional source of moisture. This may present an additional risk, which should be evaluated." And it talks about derating if
Electronics Forum | Wed Oct 06 08:41:42 EDT 1999 | Dave F
| | Hi, | | | | Help! Could anyone help to enlighten me on this? | | | | Question: | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z that using a n
Electronics Forum | Wed Oct 06 00:26:04 EDT 1999 | Karlin
| Hi, | | Help! Could anyone help to enlighten me on this? | | Question: | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z that using a normal water cl
Electronics Forum | Fri Oct 08 02:31:07 EDT 1999 | Brian
| | | | Hi, | | | | | | | | Help! Could anyone help to enlighten me on this? | | | | | | | | Question: | | | | | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowab
Electronics Forum | Wed Oct 06 12:03:12 EDT 1999 | Graham Naisbitt
| | Hi, | | | | Help! Could anyone help to enlighten me on this? | | | | Question: | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z that using a n
Electronics Forum | Wed Oct 06 23:36:28 EDT 1999 | karlin
| | | Hi, | | | | | | Help! Could anyone help to enlighten me on this? | | | | | | Question: | | | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z
Electronics Forum | Wed Oct 06 11:40:41 EDT 1999 | Debbie Alavezos
| | Hi, | | | | Help! Could anyone help to enlighten me on this? | | | | Question: | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z that using a n
