Electronics Forum | Mon Feb 21 11:22:21 EST 2000 | K. Ckak
Hi Kurt, I agree with Dave F. I had exact same problem with PBGA placement. We requested our PCB vendor to plug/tent via (button printing) after HASL with SR1000 which worked well in the long run. There are couple of failure modes associated wit
Electronics Forum | Tue Feb 19 11:08:22 EST 2002 | Chris Anglin
Guideline for Tenting Interstitial BGA Vias It is difficult to give a complete recommendation on via tenting without an idea what process conditions are required (ex: wave pass, double reflow, rework etc.). Via Pads (as Test Points) - On Bottom
Electronics Forum | Mon Apr 22 15:05:47 EDT 2002 | tim_easterling
Depending on the volume of boards you are manufacturing, the most cost effective solution would be to epoxy plug the vias prior to LPI soldermask application. The technique is common practice and most suppliers can provide it will little or no cost a
Electronics Forum | Mon Oct 18 09:41:56 EDT 1999 | Wolfgang Busko
That should not happen. There are some threads concerning BGA and wavesoldering you could look for. It�s said that you should protect the vias in the BGA-area by soldermask or at least with tented vias to prevent rereflow of BGAs solderjoints what co
Electronics Forum | Mon Jul 26 18:05:18 EDT 1999 | ScottM
| Presently protos of micro-bgas (80i/o) pitch .030/.031 | 12BGA per assembly | | The board is a (.062, 4 layers) FR-4 using Dry film | Pads .014inch | Vias within footprint .020inch | Vias to be filled by bottom side(solder side) only .030in dia. F
Electronics Forum | Tue Sep 07 12:45:47 EDT 1999 | Brad Kendall
| Could someone shares their experience on the causes of 'Open' in the BGA after reflow. | | Are you having a problem with the joint openning up after reflow. Like it was soldered after the reflow process, but at final test is not? I had this pr
Electronics Forum | Sat Sep 18 12:10:19 EDT 2004 | Steve Gregory
I have a question about solder masking via's in a BGA pattern, and want to see if I'm thinking correctly about this. This problem is kind of along the same line as Carol's problem earlier. I think it's a bad idea to leave the via's free from solder
Electronics Forum | Tue Mar 13 16:05:30 EST 2001 | rob_thomas
Hi, can you definitely attribute the 30%yield to poor bga soldering? What is your high flyer defect encountered on the failed boards.Is this ICT ,flying probe ,functional test yield? Can you determine a defect pattern? Did your subcontractor provided
Electronics Forum | Thu Feb 07 11:59:48 EST 2002 | Ron Costa
When double sided BGA's are used on an .062 FR4 10 layer board should via's be plugged and tented? The CACHE chips being used are PBGA's 1.27mm pitch. The pad size is .030 and the finished via dia. is .010. This is a dogbone type pad and via design.
Electronics Forum | Mon Oct 21 19:17:23 EDT 2013 | hegemon
The first picture shows an issue. Note that the vias adjacent to the interior rows are filled with solder. At the outside rows this is not evident. What you might have are interior spheres that are smaller in volume than the rows on the outide, si
