Industry News | 2018-02-22 05:13:27.0
Zuken® and XJTAG® have released a free plugin that will enhance Zuken’s CR-8000 Design Gateway with a design for test (DFT) capability improving test coverage by allowing additional design checks during schematic entry.
Industry News | 2020-09-10 11:16:53.0
Two Indium Corporation experts will present technical content during IMAPS International Symposium on Microelectronics, a global virtual event, Oct. 5-8.
Industry News | 2023-08-29 07:11:55.0
Indium Corporation® will showcase selections from its portfolio of proven products for thermal management and power electronics applications at SEMICON Taiwan, September 6‒8, in Taipei. In addition, Senior Area Technical Manager Jason Chou will deliver a presentation, The Lead-Free Materials Evolution in Power Die-Attach Soldering Applications, on September 7.
Industry News | 2022-03-22 16:06:45.0
XJTAG®, a leader in JTAG boundary scan products, announces a new software release that speeds up the development and debugging of boundary scan setups, and also helps to stop production line operators being distracted by too much information when they run tests.
Electronics Forum | Wed Aug 20 17:05:42 EDT 2008 | naynayno
We have experienced contamination under flat chip arrays. The lab report is still open but it appears to be dendrite growth. We have been trouble-shooting our process and cleaning equipment. My question is are there any specific design or best p
Electronics Forum | Wed Aug 20 20:10:30 EDT 2008 | davef
Naw, accounting is boring. Standoff could be an issue. Coupla things: * Above 30 thou, just about any cleaning process, more sophisticated than a garden hose, will produce acceptable results * Below 10 thou, can be cleaned with best efforts, but not
Electronics Forum | Thu Aug 21 08:15:07 EDT 2008 | naynayno
Thanks Dave, I will be sticking with Manufacturing Engineering. These are good guidelines but what is standard clearance for various packages? This is a dimension we usually seek by eye, whether we will have a problem or not. We use straight DI -
Electronics Forum | Thu Aug 21 08:33:09 EDT 2008 | davef
There is no standard as such. It's easy to see why. It's too complicated and has such a small payoff. Standoff is comprised of: * Package height * Solder thickness between the pad and the component lead * Delta of pad thickness and solder mask For p
Electronics Forum | Wed Apr 26 08:13:47 EDT 2017 | spoiltforchoice
MSL 1 is unlimited factory floor time before reflow. I have spools that are 10+ years old and haven't encountered any issues using those parts. It goes without saying those parts are not exactly used in volume so its not a massive sample but that is
Electronics Forum | Thu Apr 12 01:23:04 EDT 2001 | Eric C
Check the pad size. I had this issue before due to the pad size too wide. R&D had change the size of the pad and is solve the issue. Before the pad size change, I had rebuild another stencil with the pad opening close to the component size. It won't
