Technical Library | 2023-01-17 17:22:28.0
The impact of voiding on the solder joint integrity of ball grid arrays (BGAs)/chip scale packages (CSPs) can be a topic of lengthy and energetic discussion. Detailed industry investigations have shown that voids have little effect on solder joint integrity unless they fall into specific location/geometry configurations. These investigations have focused on thermal cycle testing at 0°C-100°C, which is typically used to evaluate commercial electronic products. This paper documents an investigation to determine the impact of voids in BGA and CSP components using thermal cycle testing (-55°C to +125°C) in accordance with the IPC- 9701 specification for tin/lead solder alloys. This temperature range is more typical of military and other high performance product use environments. A proposed BGA void requirement revision for the IPC-JSTD-001 specification will be extracted from the results analysis.
Technical Library | 2023-01-17 17:27:13.0
Reflow profile has significant impact on solder joint performance because it influences wetting and microstructure of the solder joint. The degree of wetting, the microstructure (in particular the intermetallic layer), and the inherent strength of the solder all factor into the reliability of the solder joint. This paper presents experimental results on the effect of reflow profile on both 63%Sn 37%Pb (SnPb) and 96.5%Sn 3.0%Ag 0.5%Cu (SAC 305) solder joint shear force. Specifically, the effect of the reflow peak temperature and time above solder liquidus temperature are studied. Nine reflow profiles for SAC 305 and nine reflow profiles for SnPb have been developed with three levels of peak temperature (230 o C, 240 o C, and 250 o C for SAC 305; and 195 o C, 205 o C, and 215 o C for SnPb) and three levels of time above solder liquidus temperature (30 sec., 60 sec., and 90 sec.). The shear force data of four different sizes of chip resistors (1206, 0805, 0603, and 0402) are compared across the different profiles. The shear force of the resistors is measured at time 0 (right after assembly). The fracture surfaces have been studied using a scanning electron microscopy (SEM) with energy dispersive spectroscopy (EDS)
Technical Library | 2023-01-17 17:58:36.0
Heterogeneous integration has become an important performance enabler as high-performance computing (HPC) demands continue to rise. The focus to enable heterogeneous integration scaling is to push interconnect density limit with increased bandwidth and improved power efficiency. Many different advanced packaging architectures have been deployed to increase I/O wire / area density for higher data bandwidth requirements, and to enable more effective die disaggregation. Embedded Multi-die Interconnect Bridge (EMIB) technology is an advanced, cost-effective approach to in-package high density interconnect of heterogeneous chips, providing high density I/O, and controlled electrical interconnect paths between multiple dice in a package. In emerging architectures, it is required to scale down the EMIB die bump pitch in order to further increase the die-to-die (D2D) communication bandwidth. Aa a result, bump pitch scaling poses significant challenges in the plated solder bump reflow process, e.g., bump height / coplanarity control, solder wicking control, and bump void control. It's crucial to ensure a high-quality solder bump reflow process to meet the final product reliability requirements. In this paper, a combined formic acid based fluxless and vacuum assisted reflow process is developed for fine pitch plated solder bumping application. A high-volume production (HVM) ready tool has been developed for this process.
Industry News | 2013-08-15 20:58:22.0
Heller Industries announced today that they have entered into a joint development agreement with International Business Machines Corporation (NYSE: IBM), to collaborate on the development of fluxless mass reflow furnace equipment and process for high volume manufacturing. The fluxless process utilizes gas phase formic acid to replace standard fluxing agents, and eliminates the need for pre-reflow fluxing and post-reflow flux cleanup steps.
Technical Library | 2024-03-19 15:53:34.0
Underfill is a composite material usually made of an epoxy polymer that fills gaps between a chip and its carrier or a finished package and the PCB substrate to connect the chip to the board.
Industry News | 2021-04-19 03:58:42.0
Whizz Systems, Inc., the award-winning premier provider of electronics product design, development, and manufacturing services located in the heart of the Silicon Valley, today announced the appointment of Humza Babar as its new Marketing Associate.
Training Courses | | | IPC-7711/7721 Specialist (CIS) Recert.
The Certified IPC-7711/7721 Specialist (CIS) recertification courses are intended for those individuals who were previously certified as IPC-7711/7721 Specialist.
Training Courses | | | IPC-7711/7721 Trainer (CIT)
The Certified IPC-7711/7721 Trainer (CIT) courses recognize individuals as qualified trainers in the area of rework and repair of printed boards and electronic assemblies and prepares them to deliver Certified IPC-7711/7721 (CIS) training.
Training Courses | | | IPC-7711/7721 Trainer (CIT) Recert.
The Certified IPC-7711/7721 Trainer (CIT) recertification courses are intended for those individuals who were previously accredited to provide Certified IPC-7711/7721 Trainer (CIS) training.
Industry News | 2003-06-18 07:56:46.0
The IPC-9850 test materials kit includes all the materials needed for manufacturers to test flexible placement machines and chip shooters to the specifications of the IPC-9850 standard.
