Technical Library | 2014-03-06 19:04:07.0
Over the last few years, there has been an increase in the rate of Head-in-Pillow component soldering defects which interrupts the merger of the BGA/CSP component solder spheres with the molten solder paste during reflow. The issue has occurred across a broad segment of industries including consumer, telecom and military. There are many reasons for this issue such as warpage issues of the component or board, ball co-planarity issues for BGA/CSP components and non-wetting of the component based on contamination or excessive oxidation of the component coating. The issue has been found to occur not only on lead-free soldered assemblies where the increased soldering temperatures may give rise to increase component/board warpage but also on tin-lead soldered assemblies.
Technical Library | 2023-09-18 14:10:01.0
As with many advancements in the electronics industry, consumer electronics is driving the trends for electronic packaging technologies toward reducing size and increasing functionality. Microelectronics meeting the technology needs for higher performance, reduced power consumption and size, and off the- shelf availability. Due to the breadth of work being performed in the area of microelectronics packaging/components, this report limits it presentation to board design, manufacturing, and processing parameters on assembly reliability for leadless (e.g., quad flat no-lead (QFN) or a generic term of bottom termination component (BTC)) packages. This style of package was selected for investigation because of its significant growth, lower cost, and improved functionality, especially for use in an RF application.
Technical Library | 2018-10-03 20:41:44.0
Voids in solder joints plague many electronics manufacturers. Do you have voids in your life? We have good news for you, there are many excellent ways to "Fill the Void." This paper is a continuation of previous work on voiding in which the following variables were studied: water soluble lead-free solder pastes, a variety of stencil designs, and reflow profiles. Quad Flat No-Lead (QFN) component thermal pads were used as the test vehicle. The voiding results were summarized and recommendations were made for reduction of voiding.
Industry News | 2008-05-30 16:14:19.0
The brand-new facility will be located in the heart of the Silicon Valley in Newark, CA, and is scheduled to open June 5th, 2008. phoenix|x-ray will celebrate this important milestone on June 5th, 2008 with an open house and technical symposium at the new site.
Industry News | 2024-09-30 20:02:53.0
PEMTRON is pleased to announce its participation in NEPCON Nagoya 2024, where it will showcase its cutting-edge equipment designed for precision inspection in semiconductor and electronics manufacturing. From October 23-25, visitors to PEMTRON's booth will experience demonstrations of the JUPITER 3D X-ray Inspection System, POSEIDON Wafer Warpage Measurement and FC-BGA Bump Inspection System, APOLLON Package Inspection System, and the 8800WIR Wafer Inspection System.
Industry News | 2019-07-17 19:57:39.0
At Viscom's Technology Forum this year on June 5-6 in Hanover, Germany, board member Carsten Salewski welcomed all present participants, who then debated "The Future of Electronics Manufacturing" together with outstanding speakers. Viscom sales engineer Michael Mügge moderated the forum.
Electronics Forum | Thu Jun 29 11:08:55 EDT 2000 | Dave F
Kok Han: Good to hear from you. Please help us understand you situation better by talking more about: � Component IC of the RF unit (IC101). For instance: SMT / PTH, package, pitch, lead material, lead finish, package type, package weight, coplan
Electronics Forum | Fri Jun 24 07:02:35 EDT 2005 | davef
Problem 1: Solder shortage * Stencil aperatures [except the heat slug] should be 1:1 with the board. * Stencil should be 5 thou thick laser cut. * Board should be 1:1 with the component * Print should look good. Problem #2: Bad connection between p
Electronics Forum | Mon Sep 22 17:02:58 EDT 2008 | hegemon
You are on the right track Ismir. Essentially however, as the programmer of the machine, I am the one that creates the PCB with the errors to benchmark the settings for the machine. No secret lab though! :-) Easy enough for most any AOI machine to
