Industry Directory | Manufacturer
NEW Thermally Managed, CTE controlled, Very Rigid, Light Weight STABLCOR PCB / Substrate Technology
Parts & Supplies | Circuit Board Assembly Products
1). FR-4 Tg170, Lead-free, Low Z-axis CTE, Low water absorption. 2). Excellent thermal stability and anti-CAF performance 3). 2-30 layer, 1.6mm thick 4). 1 oz copper finished 5). 10% impedance control 6). Immersion gold, HASL LF. 7). Suitable for hig
Technical Library | 2008-11-13 00:06:32.0
The electronics industry is facing issues with hot spots, solder joint stresses and Coefficient of Thermal Expansion (CTE) mismatch between PCB and IC substrate. Flip chip type packages for example have very low CTE compared to traditional PCB material. Thus it is necessary to have low CTE printed circuit boards in order to keep solder joint intact with such low CTE packages. There are currently several materials available in the market to address thermal and CTE challenges but each material has its own advantages and limitations...
MMCC manufacturers light weight, high conductivity, low expansion graphite fiber reinforced aluminum and copper alloys. These alloys are fast machining, non magnetic, non toxic, and are easily plated. CTE's from 3-15 ppm/C and K's from 180-300 W/mK.
Zymet's underfill encapsulants for flip chips are designed to enhance the thermal cycle performance. They incorporate silica filler, used to reduce the encapsulant’s CTE, that are highly engineered in both morphology and particle size distribution to
Industry Directory | Manufacturer
Thermally Managed ( up to 1000 W /m K thermal transfer rate ), CTE controlled, Very Rigid, Light Weight STABLCOR PCB / Substrate Technology
Si-Al alloy with a CTE of 6.7ppm/C. This can be supplied as plate or block, or machined and plated to a finished component. Used in satellite microwave packages, avionics, PCIMs etc.
As above with a CTE of 11ppm/C. More robust material that is used for structural applications, housings etc.
Technical Library | 2020-01-01 17:06:52.0
The majority of electronic failures occur due to thermally induced stresses and strains caused by excessive differences in coefficients of thermal expansion (CTE) across materials.CTE mismatches occur in both 1st and 2nd level interconnects in electronics assemblies. 1st level interconnects connect the die to a substrate. This substrate can be underfilled so there are both global and local CTE mismatches to consider. 2nd level interconnects connect the substrate, or package, to the printed circuit board (PCB). This would be considered a "board level" CTE mismatch. Several stress and strain mitigation techniques exist including the use of conformal coating.
