Full Site - : enig poor solder flow (Page 12 of 16)

Re: Off Pad Printing

Electronics Forum | Wed Jun 30 09:33:11 EDT 1999 | Earl Moon

| | | | | | snip | | | | | | | John and Dave, | | | | | | | | Again, I don't work with larger chip devices with this issue. The company I now work with developed a strategy, based on considerable research (as others of us did in the past), to do t

Re: AQL values....how low can you go ?

Electronics Forum | Mon Oct 25 15:45:11 EDT 1999 | Dave F

Joe: Lemme see, you�re talking about controlling your manufacturing process within 4.6 defects per 100 opportunities or a 4,600 dpmo rate, a cumulative 99.95 acceptance rate, or a �2 sigma process, right? So, it�s fairly basic stuff, eh? First, yo

Re: Solder paste SPC analysis

Electronics Forum | Thu Oct 26 17:53:32 EDT 2000 | Dave F

John: I�m here. On "what do ya think about that one!..."??? Mutha, that sounds rat�s rump [as Dennis Miller says] ugly. On some boards, we paste a cuppla chips on the break-away panels and then torque the chips from the board after cure. We use the

Re: SRT BGA Rework

Electronics Forum | Wed Dec 23 11:11:07 EST 1998 | john watt

| | I have been developing a BGA Process and are having problems with a 310 IO PBGA reflowing. I am achieving good wetting exept 2 to 5 balls on the outer perimeter I have a good profile my air flow is set per mfg spec, the strange thing is that it d

Re: Wave Solder Problems - VIA HOLES

Electronics Forum | Mon Jun 07 12:22:44 EDT 1999 | Chrys Shea

| I'm encountering a new problem at my new company that I haven't encountered before in my past life - and that's Wave Soldering VIA holes. | | We've been getting a rash of defects that we call in this company, "insufficient solder in VIA hole." The

Re: SRT BGA Rework

Electronics Forum | Fri Dec 18 10:18:55 EST 1998 | Dave F

| I have been developing a BGA Process and are having problems with a 310 IO PBGA reflowing. I am achieving good wetting exept 2 to 5 balls on the outer perimeter I have a good profile my air flow is set per mfg spec, the strange thing is that it doe

Re: Tinning gold plated leads ( DIP, etc)

Electronics Forum | Tue Mar 21 20:25:30 EST 2000 | Dave F

John: What�s the matter? Free gold � good thing for you, bad thing for your supplier. :^) Pre-tinning of gold plated leads is important to: � Prevent gold embrittlement of the solder joint � Determine if the leads are solderable prior to assembly (

Re: Wave Solder Problems - VIA HOLES

Electronics Forum | Fri Jun 04 15:51:36 EDT 1999 | JohnW

| | | I'm encountering a new problem at my new company that I haven't encountered before in my past life - and that's Wave Soldering VIA holes. | | | | | | We've been getting a rash of defects that we call in this company, "insufficient solder in VI

Re: Wave Solder Problems - VIA HOLES

Electronics Forum | Tue Jun 08 11:54:17 EDT 1999 | Steve Skinner

| | | I'm encountering a new problem at my new company that I haven't encountered before in my past life - and that's Wave Soldering VIA holes. | | | | | | We've been getting a rash of defects that we call in this company, "insufficient solder in VI

Re: Bottom side bridging

Electronics Forum | Wed Apr 15 15:04:18 EDT 1998 | D. Lange

| | | | We are having a bridging problem with SOIC 14,16 and 20 pin devices during flow solder of the bottom side of our boards. This bridging occurs about half way up the lead between the board and the body of the IC. The chip parts are no proble


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