Electronics Forum | Wed Jun 30 15:24:23 EDT 1999 | Earl Moon
| | | | | | | | | | | | | | snip | | | | | | | | | | | | | | | John and Dave, | | | | | | | | | | | | | | | | Again, I don't work with larger chip devices with this issue. The company I now work with developed a strategy, based on considerable res
Electronics Forum | Wed Jun 30 17:52:06 EDT 1999 | JohnW
| | | | | | | | | | | | | | | | snip | | | | | | | | | | | | | | | | | John and Dave, | | | | | | | | | | | | | | | | | | Again, I don't work with larger chip devices with this issue. The company I now work with developed a strategy, based on cons
Electronics Forum | Mon Jul 17 13:37:35 EDT 2006 | carln
Here is something I copied from Circuitnet.com. This appears to answer your question and then some... http://www.circuitnet.com/experts/ Ask the Experts Jul 17, 2006 What type of cleaner method is preferred for lead-free stencils? What type of s
Electronics Forum | Mon May 14 17:12:20 EDT 2001 | davef
Continuing along the path that Brian took ... IPC-7525 gives design guideline for stepped stencils. It goes something like: * Stepped area SB GT 25 thou from pads located on the greatest thickness of the stencil * Pads in stepped area SB GT 35 tho
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