Industry Directory | Consultant / Service Provider / Manufacturer
Trusted EMS Manufacturer, ISO9001, ISO14001, UL, RoHS, REACH Cheap PCB Assembly, No MOQ, Min Device 01005 HDI PCB from 4-20 Layers, Anylayer Build-up, BGA 0.25mm Quickturn Delivery Supported by 3 Plants
Used SMT Equipment | AOI / Automated Optical Inspection
Offered systems: 2 x Configurations, consisted from: M22XDL460 AOI ,Power Mac G5 PC, Monitor 17” Vantage: 2006 Condition: good. Marantz Aoi Systems •Automatic Optical Inspection of PCB’s •Inspects: SMT & THT Components (presence, type, polari
Industry News | 2012-10-22 15:54:35.0
Viscom announces that it was awarded a 2012 Global Technology Award in the category of Best Product – Europe for its SPI-AOI Uplink Feature.
Industry News | 2013-03-07 06:42:15.0
Viscom announces that it has been awarded a 2013 NPI Award in the category of Software – Process Control for its SPI-AOI Uplink function.
Vantage™ S22 Plus is a cost-effective solution that delivers top-of-the-line AOI performance to help you achieve outstanding operational efficiency and high first-pass yield in even the most demanding SMT / PTH environments. DPIX™ 3-D Technology
Watch CyberOptics' CX150i Automated Conformal Coating Inspection System in action. The CX150i offers fast and accurate conformal coating defect detection critical for long-term PCB reliability. It not only speeds up inspection but also reduces labor
LSMO-105 fastest and most reliable stencil inspection machine www.aoivision.com
Career Center | EDEN PRAIRIE, Minnesota USA | Production
Logic PD collaborates with clients to help them launch products that accelerate growth and capture value in the Internet of Things (IoT). Logic PD helps at any stage in the product lifecycle by being the complete product innovation and product realiz
Used SMT Equipment | AOI / Automated Optical Inspection
Offered systems: 2 x Configurations, consisted from: M22XDL460 AOI ,Power Mac G5 PC, Monitor 17” Vantage: 2006 Condition: good. Marantz Aoi Systems •Automatic Optical Inspection of PCB’s •Inspects: SMT & THT Components (presence, type, polari
Technical Library | 2020-07-08 20:05:59.0
There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.