Full Site - : failure modes (Page 11 of 40)

Addressing the Challenge of Head-In-Pillow Defects in Electronics Assembly

Technical Library | 2013-12-27 10:39:21.0

The head-in-pillow defect has become a relatively common failure mode in the industry since the implementation of Pb-free technologies, generating much concern. A head-in-pillow defect is the incomplete wetting of the entire solder joint of a Ball-Grid Array (BGA), Chip-Scale Package (CSP), or even a Package-On-Package (PoP) and is characterized as a process anomaly, where the solder paste and BGA ball both reflow but do not coalesce. When looking at a cross-section, it actually looks like a head has pressed into a soft pillow. There are two main sources of head-in-pillow defects: poor wetting and PWB or package warpage. Poor wetting can result from a variety of sources, such as solder ball oxidation, an inappropriate thermal reflow profile or poor fluxing action. This paper addresses the three sources or contributing issues (supply, process & material) of the head-in-pillow defects. It will thoroughly review these three issues and how they relate to result in head-in pillow defects. In addition, a head-in-pillow elimination plan will be presented with real life examples will be to illustrate these head-in-pillow solutions.

Indium Corporation

Reliability Screening of Lower Melting Point Pb-Free Alloys Containing Bi

Technical Library | 2015-07-01 16:51:43.0

Aerospace and military companies continue to exercise RoHS exemptions and to intensively research the long term attachment reliability of RoHS compliant solders. Their products require higher vibration, drop/shock performance, and combined-environment reliability than the conventional SAC305 alloy provides. The NASA-DoD Lead-Free Electronics Project confirmed that pad cratering is one of the dominant failure modes that occur in various board level reliability tests, especially under dynamic loading. One possible route to improvement of the mechanical and thermo-mechanical properties of solder joints is the use of Pb-free solders with lower process temperatures. Lower temperatures help reduce the possibility of damaging the boards and components, and also may allow for the use of lower Tg board materials which are less prone to pad cratering defects. There are several Sn-Ag-Bi and Sn-Ag-Cu-Bi alloys which melt about 10°C lower than SAC305. The bismuth in these solder compositions not only reduces the melting temperature, but also improves thermo-mechanical behavior. An additional benefit of using Bi-containing solder alloys is the possibility to reduce the propensity to whisker growth

Honeywell International

Design Parameters Influening Reliability of CCGA Assembly; a Sensitivity Analysis

Technical Library | 2019-07-30 15:29:50.0

Area Array microelectronic packages with small pitch and large I/O counts are now widely used in microelectronics packaging. The impact of various package design and materials/process parameters on reliability has been studied through extensive literature review. Reliability of Ceramic Column Grid Array (CCGA) package assemblies has been evaluated using JPL thermal cycle test results (-50°/75°C, -55°/100°C, and -55°/125°C), as well as those reported by other investigators. A sensitivity analysis has been performed using the literature data to study the impact of design parameters and global/local stress conditions on assembly reliability. The applicability of various life-prediction models for CCGA design has been investigated by comparing model's predictions with the experimental thermal cycling data. Finite Element Method (FEM) analysis has been conducted to assess the state of the stress/strain in CCGA assembly under different thermal cycling, and to explain the different failure modes and locations observed in JPL test assemblies.

Jet Propulsion Laboratory

Paragon™ Bond Testing Software

Paragon™ Bond Testing Software

New Equipment | Test Equipment - Bond Testers

Nordson DAGE’s intelligent bond testing software Paragon™ takes bond testing to the next level. Its highly intuitive and configurable interface provides quick and easy access to advanced functionality, such as automatic GR&R calculation, built-in dia

Nordson DAGE

Soldering, Coating, Cleaning and PCB Process Failures from the Desk of Bob Willis

Industry News | 2018-03-25 13:21:16.0

The widest selection of online webinars in the industry has added more titles

ASKbobwillis.com

Progressive Failure Analysis of Laminates with Embedded Wrinkle Defects Based on an Elastoplastic Damage Model

Technical Library | 2021-03-04 15:16:27.0

Out-of-plane wrinkling has a significant influence on the mechanical performance of composite laminates. Numerical simulations were conducted to investigate the progressive failure behavior of fiber-reinforced composite laminates with out-of-plane wrinkle defects subjected to axial compression. To describe the material degradation, a three-dimensional elastoplastic damage model with four damage modes (i.e., fiber tensile failure, matrix failure, fiber kinking/splitting, and delamination) was developed based on the LaRC05 criterion. To improve the computational efficiency in searching for the fracture angle in the matrix failure analysis, a high-efficiency and robust modified algorithm that combines the golden section search method with an inverse interpolation based on an existing study is proposed.

Jinan University

SMT Supervisor

Career Center | Williamsport, Pennsylvania USA | Engineering,Management

PRIMUS Technologies Corporation is an electronic manufacturing services (EMS) provider that produces highly reliable products for global government and commercial markets. Our company is an integrated lean enterprise that fully embodies the Six Sigma

PRIMUS Technologies Corp

SMT Process Engineer

Career Center | Wellsboro, Pennsylvania USA | Engineering

SMT PROCESS ENGINEER: (Wellsboro, PA) - Designs, defines and plans the manufacturing process. Specifies and directs installation of new processes. Plans equipment build schedules and monitors vendor progress. Defines and recommends equipment, methods

Truck-Lite Co., LLC

Archive Webinar Recordings on Soldering, PCB Assembly & Inspection

Industry News | 2017-03-06 05:25:35.0

Many of the webinars we present every month are available from our online archive. The video recordings and a copy of the slides can be provided for you or why not organise an education session with members of your team in a conference room so you can also discuss the subject after the session to implement your process improvements

ASKbobwillis.com

A Study on Effects of Copper Wrap Specifications on Printed Circuit Board Reliability

Technical Library | 2021-07-20 20:02:29.0

During the manufacturing of printed circuit boards (PCBs) for a Flight Project, it was found that a European manufacturer was building its boards to a European standard that had no requirement for copper wrap on the vias. The amount of copper wrap that was measured on coupons from the panel containing the boards of interest was less than the amount specified in IPC-6012 Rev B, Class 3. To help determine the reliability and usability of the boards, three sets of tests and a simulation were run. The test results, along with results of simulation and destructive physical analysis, are presented in this paper. The first experiment involved subjecting coupons from the panels supplied by the European manufacturer to thermal cycling. After 17 000 cycles, the test was stopped with no failures. A second set of accelerated tests involved comparing the thermal fatigue life of test samples made from FR4 and polyimide with varying amounts of copper wrap. Again, the testing did not reveal any failures. The third test involved using interconnect stress test coupons with through-hole vias and blind vias that were subjected to elevated temperatures to accelerate fatigue failures. While there were failures, as expected, the failures were at barrel cracks. In addition to the experiments, this paper also discusses the results of finite-element analysis using simulation software that was used to model plated-through holes under thermal stress using a steady-state analysis, also showing the main failure mode was barrel cracking. The tests show that although copper wrap was sought as a better alternative to butt joints between barrel plating and copper foil layers, manufacturability remains challenging and attempts to meet the requirements often result in features that reduce the reliability of the boards. Experimental and simulation work discussed in this paper indicate that the standard requirements for copper wrap are not contributing to the overall board reliability, although it should be added that a design with a butt joint is going to be a higher risk than a reduced copper wrap design. The study further shows that procurement requirements for wrap plating thickness from Class 3 to Class 2 would pose little risk to reliability (minimum 5 μm/0.197 mil for all via types).Experimental results corroborated by modeling indicate that the stress maxima are internal to the barrels rather than at the wrap location. In fact, the existence of Cu wrap was determined to have no appreciable effect on reliability.

NASA Office Of Safety And Mission Assurance


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