The JacketStrip 8310 axially and radially slits the insulation of out-of-round and multi-conductor cables from 0.1" - 1'' (2.5 - 25 mm) O.D. and up to 19.7" (500 mm) in stripping length without any damage to the inner conductors or shielding.
Industry News | 2013-03-27 15:21:59.0
PNC Inc. is proud to announce its latest UL qualification of polyimide base materials. PNC has partnered with Ventec USA using VT-901 laminate and VT-901PP prepreg. These high-temperature, high-reliability products expand PNC’s wide product offering and introduces the manufacturer into new industries at a new competitive level. The qualification includes 0.002” inner layer cores and a minimum overall board thickness stack up of 0.025”. The qualification also includes a minimum outer layer copper thickness of half ounce copper while inner layer maximum is two ounce copper.
Technical Library | 2015-08-20 15:18:38.0
Increasing system integration and component densities continue to significantly reduce the opportunity to access nets using standard test points. Over time the size of test points has been drastically reduced (as small as 0.5 mm in diameter) but current product design parameters have created space and access limitations that remove even the option for these test points. Many high speed signal lines have now been restricted to inner layers only. Where surface traces are still available for access, bead probe technology is an option that reduces test point space requirements as well as their effects on high speed nets and distributes mechanical loading away from BGA footprints enabling test access and reducing the risk of mechanical defects associated with the concentration of ICT spring forces under BGA devices. Building on Celestica's previous work characterizing contact resistance associated with Pr-free compatible surface finishes and process chemistry; this paper will describe experimentation to define a robust process window for the implementation of bead probe and similar bump technology that is compatible with standard Pb-free assembly processes. Test Vehicle assembly process, test methods and "Design of Experiments" will be described. Bead Probe formation and deformation under use will also be presented along with selected results.
Technical Library | 2018-09-21 10:12:53.0
Moisture accumulates during storage and industry practice recommends specific levels of baking to avoid delamination. This paper will discuss the use of capacitance measurements to follow the absorption and desorption behaviour of moisture. The PCB design used in this work, focused on the issue of baking out moisture trapped between copper planes. The PCB was designed with different densities of plated through holes and drilled holes in external copper planes, with capacitance sensors located on the inner layers. For trapped volumes between copper planes, the distance between holes proved to be critical in affecting the desorption rate. For fully saturated PCBs, the desorption time at elevated temperatures was observed to be in the order of hundreds of hours. Finite difference diffusion modelling was carried out for moisture desorption behaviour for plated through holes and drilled holes in copper planes. A meshed copper plane was also modelled evaluating its effectiveness for assisting moisture removal and decreasing bake times. Results also showed, that in certain circumstances, regions of the PCB under copper planes initially increase in moisture during baking.
Industry News | 2003-03-19 08:38:41.0
Advancements in research into thin dielectric breakdowns and exploration in the use of high-k gate dielectrics and low-k materials as interconnects are the focus of next week's International Reliability Physics Symposium.
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Industry News | 2010-01-11 15:00:06.0
DEK has extended its popular VectorGuard® stencil portfolio with the addition of the double layer Platinum stencil, a unique stencil technology offering manufacturers a series of performance benefits over conventional screens. Launched at the Productronica exhibition in Munich, VectorGuard Double Layer Platinum stencils are an ideal solution for semiconductor applications and component manufacture, meeting the needs of production challenges requiring fine line or mixed feature sizes.
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