Technical Library | 2020-07-02 01:14:44.0
Head-in-Pillow (HIP) defects are a growing concern in the electronics industry. These defects are usually believed to be the result of several factors, individually or in combination. Some of the major contributing factors include: surface quality of the BGA spheres, activity of the paste flux, improper placement / misalignment of the components, a non-optimal reflow profile, and warpage of the components. To understand the role of each of these factors in producing head-in-pillow defects and to find ways to mitigate them, we have developed two in-house tests.
Technical Library | 2021-04-21 15:10:16.0
Voids affect the thermal characteristics and mechanical properties of a solder joint, thereby affecting the reliability of the solder interconnect. The automotive sector in particular is requiring the mitigation of solder voids in various electronic control modules to the minimum possible level. Earlier research efforts performed to decrease voids involved varying the reflow profile, paste deposit, paste alloy composition, stencil aperture, and thickness. Due to the various advantages they offer, the use of Ball Grid Array packages is common across all industry sectors. They are also prone to process voiding issues. This study was performed to determine if vacuum assisted reflow process can help alleviate the voids in area array solder joints. Test parameters in this study largely focused on vacuum pressure level and vacuum dwell time.
Technical Library | 2021-09-21 20:20:22.0
The electronics industry has been using the epoxy puck for the processing of the vast majority of electronics microsections since the 1970s. Minimal advancements have been seen in the methods used for precision micro-sections of PCBs, PCBAs, and device packages. This paper will discuss different techniques and approaches in performing precision and analytical micro-sections, which fuse the techniques and materials common in preparation of silicon wafers and bulk materials. These techniques have not only been found to produce excellent optical results, but transfer effectively to SEM for high magnification inspection and further analysis with minimal post-lapping preparation needed. Additionally, processing time is reduced primarily due to a significant reduction of bulk material removal earlier in the preparation, therefore needing less removal at later lapping steps compared to traditional sectioning methods. Additional techniques are introduced that mitigate some classic challenges experienced by technicians over the decades.
Technical Library | 2022-03-16 19:41:17.0
Creep corrosion occurs in electronics assemblies and it is reminiscent to electromigration but does not require electrical field to drive the reaction. Corrosive elements and moisture must be present for creep corrosion to occur. Sulfur is the most prominent element to cause creep corrosion in environments such as paper mills, rubber manufacturing, mining, cement manufacturing, waste water treatment etc., also including companies and locations nearby such industries. The main part of printed circuit board assembly (PCBA) to be affected is the PCB surface finish. Especially immersion silver is prone to creep corrosion, but it sometimes occurs in NiPd (lead frames), and to a lesser extent in ENIG and OSP surface finishes. As the use of immersion silver is increasing as PCB surface finish and electronics are more and more used in harsh environments, creep corrosion is a growing risk. In this paper we will present the driving forces and mechanisms as well as suitable tests and mitigation strategies against creep corrosion
Technical Library | 2022-10-31 18:35:40.0
Voids affect the thermal characteristics and mechanical properties of a solder joint, thereby affecting the reliability of the solder interconnect. The automotive sector in particular is requiring the mitigation of solder voids in various electronic control modules to the minimum possible level. Earlier research efforts performed to decrease voids involved varying the reflow profile, paste deposit, paste alloy composition, stencil aperture, and thickness. Due to the various advantages they offer, the use of Ball Grid Array packages is common across all industry sectors. They are also prone to process voiding issues. This study was performed to determine if vacuum assisted reflow process can help alleviate the voids in area array solder joints. Test parameters in this study largely focused on vacuum pressure level and vacuum dwell time.
Technical Library | 2023-02-13 19:23:18.0
Spontaneously forming tin whiskers, which emerge unpredictably from pure tin surfaces, have regained prevalence as a topic within the electronics research community. This has resulted from the ROHS-driven conversion to "lead-free" solderable finish processes. Intrinsic stresses (and/or gradients) in plated films are considered to be a primary driving force behind the growth of tin whiskers. This paper compares the formation of tin whiskers on nanocrystalline and conventional polycrystalline copper deposits. Nanocrystalline copper under-metal deposits were investigated, in terms of their ability to mitigate whisker formation, because of their fine grain size and reduced film stress. Pure tin films were deposited using matte and bright electroplating, electroless plating, and electron beam evaporation. The samples were then subjected to thermal cycling conditions in order to expedite whisker growth. The resultant surface morphologies and whisker formations were evaluated.
Technical Library | 2024-06-19 15:23:54.0
Each year the semiconductor industry routes a significant volume of devices to recycling sites for no reliability or quality rationale beyond the fact that those devices were stored on a warehouse shelf for two years. This study identifies the key risks attributed to extended storage of devices in uncontrolled indoor environments and the risk mitigation required to permit safe shelf-life extension. Component reliability was evaluated after extended storage to assure component solderability, MSL stability and die surface integrity. Packing materials were evaluated for customer use parameters as well as structural integrity and ESD properties. Results show that current packaging material (mold compound and leadframe) is sufficiently robust to protect the active integrated circuits for many decades and permit standard reflow solder assembly beyond 15 years. Standard packing materials (bags, desiccant, and humidity cards) are robust for a 32 month storage period that can be extended by repacking with fresh materials. Packing materials designed for long term storage are effective for more than five years.
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Industry News | 2005-11-03 11:14:00.0
Parvus to transition to lead-free production of embedded PC products by July 1, 2006; Parvus to focus on reliability assurance and risk mitigation techniques with high-reliability customers
