Electronics Forum | Wed Aug 01 11:03:20 EDT 2001 | Chip Gill
I read your request for design information on panel layout for V-scoring, and felt the need to respond. Scored PWB's are indeed more efficient to produce and depanel than tab routed PWB's, but there are also drawbacks associated with this method. T
Electronics Forum | Mon Nov 08 11:01:12 EST 1999 | Brian Larson
We are leaving 12-18 thousands material when scoring. Several components are cracking during depanelization. The pizza cutter machines out there are either too expensive or too slow to solve our problem. I am looking for a magical solution. In case
Electronics Forum | Mon Nov 08 19:10:10 EST 1999 | Brian W.
Oh boy, does that bring back memories!!!!! You are most likely breaking components when the board is flexed during separation. Any components perpendicular to the score are candidates for mechanical stress. We overcame the problem by making our ow
Electronics Forum | Wed Jul 15 13:33:56 EDT 1998 | Don Welling
I am looking for information on the amount of stress a component sees during the depaneling process. I am currently specifying a new piece of depaneling equipment and I have not found any studies that quantitatively compare the amount of stress diff
Electronics Forum | Tue Feb 28 16:58:39 EST 2006 | PWH
Too fast heating/cooling rate in reflow (look at mfg's spec.). Z "overdrive" on pick and place or chipshooter though unlikely I would say. Depanelization method (bending a scored board to break it is tough on things). Bad PCB design - cap. too clo
Electronics Forum | Thu May 11 17:28:40 EDT 2006 | bradlanger
Steve, We have had the same problem at my company and unfortunately I do not have any good news for you. We are using a pizza slicer type depanalizer from FKN and if the MLCC caps are layed out too close to the edge they still break. We had to add th
Electronics Forum | Mon Jun 12 17:32:17 EDT 2006 | flipit
Hi, A little off subject but I just finished a quick little experiment where I placed 0201 to 1206 and some ceramic resonators at specific distances off the scored edge. The distances from scored edge ranged from 0.025" on up at 0.025" increments.
Electronics Forum | Wed Mar 21 10:30:15 EDT 2007 | ck_the_flip
Chrissie also says, "Before anyone suggests it - redesign of the boards is not an option!!", so I'm assuming that re-design means panelization too. She's probably sitting on thousands of these unpanelized PCB's in stock. Now, for the future, as Ste
Electronics Forum | Mon Jul 30 11:08:23 EDT 2007 | swag
I have a new contract with boards that have straight edges and are good for v-score breakout panel design. However, many of the traces are very close to the edge of the board so I am concerned that the traces could be damaged when we run them throug
Electronics Forum | Thu Nov 13 11:45:04 EST 2008 | pbarton
We have seen a similar problem. Turned out to be mechanical stress on the component caused by the method of location and clamping at ICT. Where is the component located on the assembly? Poorly adjusted clamping pillars on clamshell fixtures can cause
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