4047 plug & yield results

Stencil Printing Process Tools for Miniaturisation and High Yield Processing

Technical Library | 2023-06-12 19:00:21.0

The SMT print process is now very mature and well understood. However as consumers continually push for new electronic products, with increased functionality and smaller form factor, the boundaries of the whole assembly process are continually being challenged. Miniaturisation raises a number of issues for the stencil printing process. How small can we print? What are the tightest pitches? Can we print small deposits next too large for high mix technology assemblies? How closely can we place components for high density products? ...And then on top of this, how can we satisfy some of the cost pressures through the whole supply chain and improve yield in the production process! Today we are operating close to the limits of the stencil printing process. The area ratio rule (the relationship between stencil aperture opening and aperture surface area) fundamentally dictates what can and cannot be achieved in a print process. For next generation components and assembly processes these established rules need to be broken! New stencil printing techniques are becoming available which address some of these challenges. Active squeegees have been shown to push area ratio limits to new boundaries, permitting printing for next generation 0.3CSP technology. Results also indicate there are potential yield benefits for today's leading edge components as well. Stencil coatings are also showing promise. In tests performed to date it is becoming apparent that certain coatings can provide higher yield processing by extending the number of prints that can be performed in-between stencil cleans during a print process. Preliminary test results relating to the stencil coating technology and how they impact miniaturisation and high yield processing will be presented.

ASM Assembly Systems (DEK)