Industry News | 2012-12-10 23:38:21.0
Mentor Graphics announced the availability of its latest Mentor® Embedded Sourcery™ VSIPL++ product. The Sourcery VSIPL++ product adds support for ARM v7 Cortex A with NEON single instruction, multiple data (SIMD) processing platforms, and an interface to MATLAB® for signal and image processing algorithm conversion.
Industry News | 2018-12-08 03:29:29.0
SMT Dictionary – Surface Mount Technology Acronym and Abbreviation
Industry News | 2013-02-01 15:00:00.0
Mentor Graphics announced the newest release of its market-leading HyperLynx® product for superior high-speed design and analysis. Key features in the new HyperLynx product release include advanced 3D channel and trace modeling, improved DDR signoff verification, and accelerated simulation performance—up to 5X faster.
Industry News | 2016-02-03 12:04:47.0
The theme for Seica at Apex this year will be automation and Industry 4.0. Highlights will include the traditional Compact line of bed of nails and functional testers; the Pilot line, a truly versatile and multi-faceted flying probe system; its Mini line of benchtop ATE, and the Firefly line, a premier laser selective soldering system.
Technical Library | 2023-07-25 16:50:02.0
Some of the new handheld communication devices offer real challenges to the paste printing process. Normally, there are very small devices like 01005 chip components as well as 0.3 mm pitch uBGA along with other devices that require higher deposits of solder paste. Surface mount connectors or RF shields with coplanarity issues fall into this category. Aperture sizes for the small devices require a stencil thickness in the 50 to 75 um (2-3 mils) range for effective paste transfer whereas the RF shield and SMT connector would like at least 150 um (6 mils) paste height. Spacing is too small to use normal step stencils. This paper will explore a different type of step stencil for this application; a "Two-Print Stencil Process" step stencil. Here is a brief description of a "Two-Print Stencil Process". A 50 to 75 um (2-3 mils) stencil is used to print solder paste for the 01005, 0.3 mm pitch uBGA and other fine pitch components. While this paste is still wet a second in-line stencil printer is used to print all other components using a second thicker stencil. This second stencil has relief pockets on the contact side of the stencil any paste was printed with the first stencil. Design guidelines for minimum keep-out distances between the relief step, the fine pitch apertures, and the RF Shields apertures as well relief pocket height clearance of the paste printed by the first print stencil will be provided.
Industry News | 2020-10-16 02:24:55.0
SunzonTech PCB shuttle conveyor
Technical Library | 2021-12-16 01:52:32.0
Package on Packages (PoP) find use in applications that require high performance with increased memory density. One of the greatest benefits of PoP technology is the elimination of the expensive and challenging task of routing high-speed memory lines from under the processor chip out to memory chip in separate packages. Instead, the memory sits on top of the processor and the connections are automatically made during assembly. For this reason PoP technology has gained wide acceptance in cell phones and other mobile applications. PoP technology can be assembled using one-pass and two-pass assembly processes. In the one-pass technique the processor is first mounted to the board, the memory is mounted to the processor and the finished board is then run through the reflow oven in a single pass. The two-pass technique has an intermediate step in which the memory is first mounted onto the processor.
Industry News | 2009-09-30 10:58:26.0
SMTrue Run Optimize Software incorporates Universal CAD Translator with powerful new functionality for off-line job and feeder set-up, programming, optimization, and management.
Industry News | 2002-05-14 09:08:43.0
SMEMA Compliant Solution to be Developed for Wafer Bumping Screen Printers
Technical Library | 2019-07-17 17:56:34.0
The increased demand for electronic devices in recent years has led to an extensive research in the field to meet the requirements of the industry. Electrolytic copper has been an important technology in the fabrication of PCBs and semiconductors. Aqueous sulfuric acid baths are explored for filling or building up with copper structures like blind micro vias (BMV), trenches, through holes (TH), and pillar bumps. As circuit miniaturization continues, developing a process that simultaneously fills vias and plates TH with various sizes and aspect ratios, while minimizing the surface copper thickness is critical. Filling BMV and plating TH at the same time, presents great difficulties for the PCB manufactures. The conventional copper plating processes that provide good via fill and leveling of the deposit tend to worsen the throwing power (TP) of the electroplating bath. TP is defined as the ratio of the deposit copper thickness in the center of the through hole to its thickness at the surface. In this paper an optimization of recently developed innovative, one step acid copper plating technology for filling vias with a minimal surface thickness and plating through holes is presented.
